用PLD设计的篮球计时计分器.docx
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用PLD设计的篮球计时计分器.docx
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用PLD设计的篮球计时计分器
用PLD设计的篮球计时计分器
一、设计原理
该篮球计时计分器,由九个功能模块组成:
时钟产生模块、按键输入模块、系统的计时模块、24秒计时模块、数码管输出模块、led输出模块、计分模块、lcd输出模块、比分交换模块
实现的主要功能:
S1、S2分别用于两队比分的减1,S3、S4分别用于两队比分的加1,S5用于控制比赛的开始和暂停,S6用于24秒的重新置位,和进入下一节的显示切换,S7用于系统的复位,S8用于对比赛总时间减一分(调试时用,实际中不需要这个按键)。
液晶屏显示比分,数码管显示一节时间和24秒倒计时;当按下S7时,系统复位,液晶屏显示000:
0001st,数码管显示120024;当按下S5时系统开始计时,若再按下S5则处于暂停状态;当24秒倒计时剩余时间小于一秒时,则显示为秒表计时方式;当24秒时间到了,则8个led灯全亮,比赛暂停,此时先按下S5再按S6则重新从24秒开始倒计时;当一节比赛结束时,8个led灯全亮,比赛暂停,此时先按下S5再按S6则进入下一节;当比赛进行到第三节时,则比分交换显示。
二、设计
1、顶层图:
2、各子模块及对应程序:
(1)数码管输出模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityshumaguanis
port(clk:
instd_logic;
ledag:
outstd_logic_vector(7downto0);
del:
outstd_logic_vector(2downto0);
m10:
instd_logic_vector(3downto0);
m:
instd_logic_vector(3downto0);
s10:
instd_logic_vector(3downto0);
s:
instd_logic_vector(3downto0);
s24_10:
instd_logic_vector(3downto0);
s24:
instd_logic_vector(3downto0));
endshumaguan;
architecturertlofshumaguanis
signalcq:
std_logic_vector(3downto0);
signaldount:
std_logic_vector(2downto0);
begin
process(clk)--数码管动态扫描
begin
if(clk'eventandclk='1')then
dount<=dount+1;
endif;
del<=dount;
endprocess;
process(dount,s24,s24_10,s,s10,m,m10)
begin
if(dount=0)then
cq<=m10;
elsif(dount=1)then
cq<=m;
elsif(dount=2)then
cq<=s10;
elsif(dount=3)then
cq<=s;
elsif(dount=4)then
cq<="1111";
elsif(dount=5)then
cq<="1111";
elsif(dount=6)then
cq<=s24_10;
elsif(dount=7)then
cq<=s24;
endif;
endprocess;
process(cq)--数码管显示
begin
casecqis
when"0000"=>ledag<="11000000";
when"0001"=>ledag<="11111001";
when"0010"=>ledag<="10100100";
when"0011"=>ledag<="10110000";
when"0100"=>ledag<="10011001";
when"0101"=>ledag<="10010010";
when"0110"=>ledag<="10000010";
when"0111"=>ledag<="11111000";
when"1000"=>ledag<="10000000";
when"1001"=>ledag<="10010000";
when"1010"=>ledag<="11111111";
when"1011"=>ledag<="11111111";
when"1100"=>ledag<="11111111";
when"1101"=>ledag<="11111111";
when"1110"=>ledag<="11111111";
when"1111"=>ledag<="11111111";
whenothers=>null;
endcase;
endprocess;
endrtl;
(2)时钟产生模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityshizhongis
port(clk:
instd_logic;
beep:
outbit;
clk_25hz,clk_100hz,clk_1khz:
outstd_logic);
endshizhong;
architecturertlofshizhongis
signalclk_100hz_s:
std_logic;
begin
process(clk_100hz_s)
variableq2:
integerrange0to9;
begin
if(clk_100hz_s='1'andclk_100hz_s'event)then
if(q2=3)then
clk_25hz<='1';
q2:
=q2+1;
elsif(q2=4)then
clk_25hz<='0';
q2:
=0;
elseclk_25hz<='0';
q2:
=q2+1;
endif;
endif;
endprocess;
process(clk)
variableq3:
integerrange0to499999;
begin
if(clk='1'andclk'event)then
if(q3=499999)then
q3:
=0;
else
if(q3<250000)then
clk_100hz<='0';
clk_100hz_s<='0';
elseclk_100hz<='1';
clk_100hz_s<='1';
endif;
q3:
=q3+1;
endif;
endif;
endprocess;
process(clk)
variableq4:
integerrange0to49999;
begin
if(clk='1'andclk'event)then
if(q4=49999)then
q4:
=0;
else
if(q4<25000)then
clk_1khz<='0';
elseclk_1khz<='1';
endif;
q4:
=q4+1;
endif;
endif;
endprocess;
beep<='1';
endrtl;
(3)led输出模块
libraryieee;
useieee.std_logic_1164.all;
entityledis
port(ledin:
instd_logic;
ledout:
outstd_logic_vector(7downto0));
endled;
architecturertlofledis
begin
process(ledin)
begin
if(ledin='0')then
ledout<="00000000";
elseledout<="11111111";
endif;
endprocess;
endrtl;
(4)lcd输出模块
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitylcdis
Port(Clk:
instd_logic;--状态机时钟信号,同时也是液晶时钟信号,其周期应该满足液晶数据的建立时间
Aout_100,Aout_10,Aout,Bout_100,Bout_10,Bout:
instd_logic_vector(3downto0);
period:
instd_logic_vector(2downto0);
LCD_RS:
outstd_logic;--寄存器选择信号
LCD_RW:
outstd_logic;--液晶读写信号
LCD_EN:
outstd_logic;--液晶时钟信号
LCD_Data:
outstd_logic_vector(7downto0));--液晶数据信号
endlcd;
architectureBehavoflcdis
typeSTATE_TYPEis(START,write_C,write_D,WRITE_BYTE_C,WRITE_BYTE_D,wait_3m1,wait_3m2,wait_5m1,wait_5m2,wait_100m);--12个状态,START:
初始化各信号量,write_C(write_D):
判断初始化指令(显示数据)是否输出完毕,WRITE_BYTE_C(WRITE_BYTE_D):
输出一个指令(数据),wait_3m1,wait_3m2,wait_5m1,wait_5m2,wait_100m:
延时
typeMY_ARRAY_Cisarray(0to4)ofstd_logic_vector(7downto0);--初始化的数据(控制指令)
typeMY_ARRAY_Disarray(0to11)ofstd_logic_vector(7downto0);
constantc_d:
MY_ARRAY_C:
=(x"38",x"0c",x"06",x"01",x"C3");
signald_d:
MY_ARRAY_D;
signalSTATE:
STATE_TYPE:
=START;
signalw_c_flag:
integerrange0to2:
=0;--写指令时用到的标志
signalw_d_flag:
integerrange0to2:
=0;--写数据时用到的标志
signalwrite_c_cnt:
integerrange0to5:
=0;--指令的指针
signalwrite_d_cnt:
integerrange0to12:
=0;--数据的指针
signalcnt:
integerrange0to100:
=0;--延时用到的计数器
begin
LCD_RW<='0';--写数据
d_d(0)<="0000"&Aout_100+x"30";
d_d
(1)<="0000"&Aout_10+x"30";
d_d
(2)<="0000"&Aout+x"30";
d_d(3)<="00111010";
d_d(4)<="0000"&Bout_100+x"30";
d_d(5)<="0000"&Bout_10+x"30";
d_d(6)<="0000"&Bout+x"30";
d_d(7)<="00100000";
d_d(8)<="00100000";
d_d(9)<="00000"&period+x"31";
d_d(10)<="01110011";
d_d(11)<="01110100";
process(Clk,STATE)--液晶驱动控制器
begin
ifrising_edge(Clk)then
caseSTATEis
whenSTART=>
LCD_EN<='0';
w_c_flag<=0;
w_d_flag<=0;
write_c_cnt<=0;
write_d_cnt<=0;
STATE<=WRITE_C;--下一个状态(即要执行的)是WRITE_C(相当于跳转)
whenWRITE_C=>
casewrite_c_cntis
when0to4=>--小于5,五个初始化指令未输出完,则要输出
STATE<=WRITE_BYTE_C;
when5=>
write_c_cnt<=0;--等于5,五个初始化指令已输出完,转入数据输出
STATE<=WRITE_D;--转入数据输出
endcase;
whenWRITE_BYTE_C=>
if(w_c_flag=0)then--w_c_flag=0,通道选择,数据输出
LCD_RS<='0';
LCD_Data<=c_d(write_c_cnt);
w_c_flag<=1;
STATE<=wait_3m1;--延时
elsif(w_c_flag=1)then--w_c_flag=1,使能en='1'
LCD_EN<='1';
w_c_flag<=2;
STATE<=wait_5m1;--延时
elsif(w_c_flag=2)then--w_c_flag=2,使能en='0'
LCD_EN<='0';
w_c_flag<=0;
write_c_cnt<=write_c_cnt+1;--当前数据已输出完,write_c_cnt加一指向下一个数据,并转入下一个数据输出WRITE_C
STATE<=WRITE_C;
endif;
whenWRITE_D=>
casewrite_d_cntis
when0to11=>
STATE<=WRITE_BYTE_D;
when12=>
write_d_cnt<=0;
STATE<=wait_100m;--所有数据输出完毕
endcase;
whenWRITE_BYTE_D=>
if(w_d_flag=0)then
LCD_RS<='1';
LCD_Data<=d_d(write_d_cnt);
w_d_flag<=1;
STATE<=wait_3m2;
elsif(w_d_flag=1)then
LCD_EN<='1';
w_d_flag<=2;
STATE<=wait_5m2;
elsif(w_d_flag=2)then
LCD_EN<='0';
w_d_flag<=0;
write_d_cnt<=write_d_cnt+1;
STATE<=WRITE_D;
endif;
whenwait_3m1=>
if(cnt>=3)then
STATE<=WRITE_BYTE_C;
cnt<=0;
else
cnt<=cnt+1;
STATE<=wait_3m1;
endif;
whenwait_5m1=>
if(cnt>=5)then
STATE<=WRITE_BYTE_C;
cnt<=0;
else
cnt<=cnt+1;
STATE<=wait_5m1;
endif;
whenwait_3m2=>
if(cnt>=3)then
STATE<=WRITE_BYTE_D;
cnt<=0;
else
cnt<=cnt+1;
STATE<=wait_3m2;
endif;
whenwait_5m2=>
if(cnt>=5)then
STATE<=WRITE_BYTE_D;
cnt<=0;
else
cnt<=cnt+1;
STATE<=wait_5m2;
endif;
whenwait_100m=>
if(cnt>=100)then
STATE<=START;--该轮次的所有数据(指令,显示)都已输出,回到START,开始新一轮的输出
cnt<=0;
else
cnt<=cnt+1;
STATE<=wait_100m;
endif;
endcase;
endif;
endprocess;
endBehav;
(5)24秒计时模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYjishi24_cnt10IS
PORT(res,en,clk:
INSTD_LOGIC;
reset:
INSTD_LOGIC;
borrow:
OUTSTD_LOGIC;
dataout:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDjishi24_cnt10;
ARCHITECTURErtlOFjishi24_cnt10IS
BEGIN
PROCESS(res,en,clk)
VARIABLEq:
INTEGERRANGE0TO9;
BEGIN
IF(res='1')THEN
q:
=0;
borrow<='0';
ELSIF(reset='1'ANDen='0')THEN
q:
=0;
borrow<='0';
ELSIF(en='1')THEN
IF(clk='1'ANDclk'EVENT)THEN
IF(q=0)THEN
q:
=9;
borrow<='1';
ELSE
q:
=q-1;
borrow<='0';
ENDIF;
ENDIF;
ENDIF;
dataout<=CONV_STD_LOGIC_VECTOR(q,4);
ENDPROCESS;
ENDrtl;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYcnt1_10IS
PORT(res,en,clk:
INSTD_LOGIC;
reset:
INSTD_LOGIC;
borrow:
OUTSTD_LOGIC;
dataout:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDcnt1_10;
ARCHITECTURErtlOFcnt1_10IS
BEGIN
PROCESS(res,en,clk)
VARIABLEq:
INTEGERRANGE0TO9;
BEGIN
IF(res='1')THEN
q:
=4;
borrow<='0';
ELSIF(reset='1'ANDen='0')THEN
q:
=4;
borrow<='0';
ELSIF(en='1')THEN
IF(clk='1'ANDclk'EVENT)THEN
IF(q=0)THEN
q:
=9;
borrow<='1';
ELSE
q:
=q-1;
borrow<='0';
ENDIF;
ENDIF;
ENDIF;
dataout<=CONV_STD_LOGIC_VECTOR(q,4);
ENDPROCESS;
ENDrtl;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYcnt_2IS
PORT(res,en,clk:
INSTD_LOGIC;
reset:
INSTD_LOGIC;
borrow:
OUTSTD_LOGIC;
dataout:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDcnt_2;
ARCHITECTURErtlOFcnt_2IS
BEGIN
PROCESS(res,en,clk)
VARIABLEq:
INTEGERRANGE0TO2;
BEGIN
IF(res='1')THEN
q:
=2;
borrow<='0';
ELSIF(reset='1'ANDen='0')THEN
q:
=2;
borrow<='0';
ELSIF(en='1')THEN
IF(clk='1'ANDclk'EVENT)THEN
IF(q=0)THEN
q:
=2;
borrow<='1';
ELSE
q:
=q-1;
borrow<='0';
ENDIF;
ENDIF;
ENDIF;
dataout<=CONV_STD_LOGIC_VECTOR(q,4);
ENDPROCESS;
ENDrtl;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymux1is
port(s1_10,s1,sec1_10,sec1,s10,s,sec10,sec:
instd_logic_vector(3downto0);
s10_out:
outstd_logic_vector(3downto0);
s_out:
outstd_logic_vector(3downto0);
ctrl_1,ctrl_2:
instd_logic;
pause:
outstd_logic;
res:
instd_logic);
endmux1;
architecturertlofmux1is
begin
process(s1_10,s
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