EDA中国地质大学 课堂作业.docx
- 文档编号:13567077
- 上传时间:2023-06-15
- 格式:DOCX
- 页数:15
- 大小:71.17KB
EDA中国地质大学 课堂作业.docx
《EDA中国地质大学 课堂作业.docx》由会员分享,可在线阅读,更多相关《EDA中国地质大学 课堂作业.docx(15页珍藏版)》请在冰点文库上搜索。
EDA中国地质大学课堂作业
1题:
4选1生成8个
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityffis
port(ain:
instd_logic_vector(3downto0);
sel:
instd_logic_vector(1downto0);
y:
outstd_logic);
end;
architecturebhvofffis
begin
y<=ain(conv_integer(sel));
endbhv;
libraryieee;
useieee.std_logic_1164.all;
packagenewtypeis
typeary84isarray(7downto0,3downto0)ofstd_logic;
typeary82isarray(7downto0,1downto0)ofstd_logic;
Endpackage;
libraryieee;
useieee.std_logic_1164.all;
usework.newtype.all;
entityfis
port(ain84:
inary84;
sel84:
inary82;
y84:
outstd_logic_vector(7downto0);
count:
outstd_logic);
end;
architecturetoffis
componentffis
port(ain:
instd_logic_vector(3downto0);
sel:
instd_logic_vector(1downto0);
y:
outstd_logic);
endcomponent;
signaly841:
std_logic_vector(7downto0);
begin
gen1:
fornin0to7generate
ux:
ffportmap(ain84(n,3)&ain84(n,2)&ain84(n,1)&ain84(n,0),
sel84(n,1)&sel84(n,0),y841(n));
endgenerate;
y84<=y841;
process(y841)
variabletmp:
std_logic;
begin
tmp:
='1';
foriin0to7loop
tmp:
=tmpandy841(i);
endloop;
count<=tmp;
endprocess;
endarchitecture;
2题:
5-4状态机
libraryieee;
useieee.std_logic_1164.all;
entityffis
port(clk,res:
instd_logic;
ina:
instd_logic_vector(0to2);
outa:
outstd_logic_vector(3downto0));
endff;
architecturef1offfis
typestais(s0,s1,s2,s3);
signalcs,ns:
sta;
begin
reg:
process(clk,res)begin
ifres='1'thencs<=s0;
elsifclk'eventandclk='1'thencs<=ns;endif;
endprocess;
com:
process(cs,ina)begin
casecsis
whens0=>ns<=s1;
ifina="101"thenouta<="0010";
elsifina="111"thenouta<="1100";
endif;
whens1=>outa<="1001";
ifina="000"thenns<=s1;
elsifina="110"thenns<=s2;elsens<=s2;
endif;
whens2=>outa<="1111";
ifina="011"thenns<=s1;
elsifina="100"thenns<=s2;
elsens<=s3;
endif;
whens3=>ns<=s0;
ifina="101"thenouta<="1101";
elsifina="011"thenouta<="1110";
endif;
endcase;
endprocess;
endarchitecture;
3题:
例题5-2
libraryieee;
useieee.std_logic_1164.all;
entityffis
port(clk,res:
instd_logic;
ina:
instd_logic_vector(0to2);
outa:
outstd_logic_vector(3downto0));
endff;
architecturef1offfis
typestais(s0,s1,s2,s3);
signalcs,ns:
sta;
begin
reg:
process(clk,res)begin
ifres='1'thencs<=s0;
elsifclk'eventandclk='1'thencs<=ns;endif;
endprocess;
com:
process(cs,ina)begin
casecsis
whens0=>ns<=s1;
ifina="101"thenouta<="0010";
elsifina="111"thenouta<="1100";
endif;
whens1=>outa<="1001";
ifina="000"thenns<=s1;
elsifina="110"thenns<=s2;elsens<=s2;
endif;
whens2=>outa<="1111";
ifina="011"thenns<=s1;
elsifina="100"thenns<=s2;
elsens<=s3;
endif;
whens3=>ns<=s0;
ifina="101"thenouta<="1101";
elsifina="011"thenouta<="1110";
endif;
endcase;
endprocess;
endarchitecture;
4题
libraryieee;
useieee.std_logic_1164.all;
entityffis
port(clk:
instd_logic;
q1,q2:
outstd_logic);
endentity;
architecturef1offfis
proceduredd(signalclk1:
instd_logic;-
signalq:
inoutstd_logic)is
begin
ifclk1'eventandclk1='1'thenq<=notq;endif;
return;
enddd;
signalqs1,qs2:
std_logic;
begin
process(clk)
begin
dd(clk,qs1);
dd(qs1,qs2);
endprocess;
q1<=qs1;
q2<=qs2;
endarchitecture;
6题显示管
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
usEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYffIS
PORT(din:
inSTD_LOGIC_VECTOR(3DOWNTO0);
cin:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDENTITY;
ARCHITECTUREFFOFffIS
BEGIN
PROCESS(din)
BEGIN
CASEdinis
WHEN"0000"=>cin<="0000001";
WHEN"0001"=>cin<="1100111";
WHEN"0010"=>cin<="1001100";
WHEN"0011"=>cin<="1000010";
WHEN"0100"=>cin<="0100110";
WHEN"0101"=>cin<="0010010";
WHEN"0110"=>cin<="0010000";
WHEN"0111"=>cin<="1000111";
WHEN"1000"=>cin<="0000000";
WHEN"1001"=>cin<="0000010";
WHENOTHERS=>cin<="1111111";
ENDCASE;
ENDPROCESS;
ENDARCHITECTURE;
7题例题7-4奇偶校验位
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYffIS
PORT(a:
inSTD_LOGIC_VECTOR(7DOWNTO0);
y:
OUTSTD_LOGIC);
ENDENTITY;
ARCHITECTUREfOFffIS
BEGIN
PROCESS(a)
variabletmp:
STD_LOGIC:
='0';
BEGIN
fornin0to7loop
tmp:
=tmpxora(n);
endloop;
y<=tmp;
ENDPROCESS;
ENDARCHITECTURE;
8题4-2编码器
libraryieee;
useieee.std_logic_1164.all;
entityffis
port(ain:
instd_logic_vector(0to3);
cin:
outstd_logic_vector(0to1));
endentity;
architecturefofffis
begin
process(ain)
begin
caseainis
when"0001"=>cin<="00";
when"0010"=>cin<="01";
when"0100"=>cin<="10";
when"1000"=>cin<="11";
whenothers=>null;
endcase;
endprocess;
endarchitecture;
9、题一位二进制全减器习题3—4
1位二进制全减器顶层设计描述
libraryieee;
useieee.std_logic_1164.all;
entityf_mis
port(x,y,subin:
instd_logic;
diffr,subout:
outstd_logic);
endentityf_m;
architecturefd1off_mis
componenth_m
port(x,y:
instd_logic;
diff,sout:
outstd_logic);
endcomponent;
signald,e,f:
std_logic;
begin
u1:
h_mportmap(x,y,d,e);
u2:
h_mportmap(d,subin,diffr,f);
subout<=eorf;
end;
半减器描述,布尔方程描述法,及或门逻辑描述
libraryieee;
useieee.std_logic_1164.all;
entityh_mis
port(x,y:
instd_logic;
diff,sout:
outstd_logic);
endentityh_m;
architecturefh1ofh_mis
begin
sout<=(notx)andy;diff<=xxory;
endarchitecturefh1;
10、二选一多路选择器:
libraryieee;
useieee.std_logic_1164.all;
entitymux21is
port(a,b,s:
instd_logic;
y:
outstd_logic);
endentity;
architectureoneofmux21is
begin
y<=awhens='0'elseb;
endarchitectureone;
11.四选一电路
libraryieee;
useieee.std_logic_1164.all;
entityx4is
port(a,b,c,d,s0,s1:
instd_logic;
y:
outstd_logic);
end;
architecturebhvofx4is
signalq:
std_logic_vector(1downto0);
begin
q<=s0&s1;
process(q)
begin
caseqis
when"00"=>y<=a;
when"01"=>y<=b;
when"10"=>y<=c;
when"11"=>y<=d;
endcase;
endprocess;
end;
3.(本题8分)信号赋值语句在什么情况下做并行语句?
在什么情况下做顺序语句?
信号赋值符号和变量赋值符号分别是什么?
两种赋值符号有什么区别?
【参考答案】:
信号赋值语句在进程外做并行语句,并发执行,与语句所处的位值无关。
2分
信号赋值语句在进程内或子程序内做顺序语句,按顺序执行,与语句所处的位值有关。
2分
信号赋值符号为“<=”。
1分
变量赋值符号为“:
=”。
1分
信号赋值符号用于信号赋值动作,不立即生效。
1分
变量赋值符号用于变量赋值动作,立即生效。
1分
1.(本题9分)门电路是构成组合逻辑电路的基本单元。
基本门电路主要包括非门、与门、与非门、或门、或非门、异或门、同或门等。
请用VHDL设计一个四输入与非门。
【参考答案】:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;--2分
ENTITYtest1IS--3分
PORT(A,B,C,D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC);
ENDtest1;
ARCHITECTUREtest1OFtest1IS--2分
BEGIN
Q<=not(AandBandCandD);--2分
ENDtest1;
2.(本题12分)优先级编码器常用于中断的优先级控制。
请用VHDL设计一个8位输入,3位编码输出的优先级编码器。
该编码器的真值表如下所示(表中“x”表示任意值,“Z”表示高阻态)。
3.LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;--2分
ENTITYtest2IS--3分
PORT(input:
INSTD_LOGIC_VECTOR(7DOWNTO0);
y:
OUTSTD_LOGIC_VECTOR(2DOWNTO0));
ENDtest2;
ARCHITECTUREtest2OFtest2IS--2分
BEGIN
PROCESS(input)--1分
BEGIN
IF(input(0)='0')THEN--2分
y<="000";
ELSIF(input
(1)='0')THEN
y<="001";
ELSIF(input
(2)='0')THEN
y<="010";
ELSIF(input(3)='0')THEN
y<="011";
ELSIF(input(4)='0')THEN
y<="100";
ELSIF(input(5)='0')THEN
y<="101";
ELSIF(input(6)='0')THEN
y<="110";
ELSIF(input(7)='0')THEN
y<="111";
ELSE
y<="ZZZ";--2分
ENDIF;
ENDPROCESS;
ENDtest2;
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- EDA中国地质大学 课堂作业 EDA 中国地质大学 课堂 作业