DDR3的TESTBENCH verilog测试代码.docx
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DDR3的TESTBENCH verilog测试代码.docx
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DDR3的TESTBENCHverilog测试代码
/****************************************************************************************
*
*FileName:
tb.v
*
`timescale1ps/1ps
moduletb;
`include"ddr3_parameters.vh"
//ports
regrst_n;
regck;
wireck_n=~ck;
regcke;
regcs_n;
regras_n;
regcas_n;
regwe_n;
reg[BA_BITS-1:
0]ba;
reg[ADDR_BITS-1:
0]a;
wire[DM_BITS-1:
0]dm;
wire[DQ_BITS-1:
0]dq;
wire[DQS_BITS-1:
0]dqs;
wire[DQS_BITS-1:
0]dqs_n;
wire[DQS_BITS-1:
0]tdqs_n;
wireodt;
//moderegisters
reg[ADDR_BITS-1:
0]mode_reg0;//ModeRegister
reg[ADDR_BITS-1:
0]mode_reg1;//ExtendedModeRegister
reg[ADDR_BITS-1:
0]mode_reg2;//ExtendedModeRegister2
wire[3:
0]cl={mode_reg0[2],mode_reg0[6:
4]}+4;//CASLatency
wirebo=mode_reg0[3];//BurstOrder
reg[3:
0]bl;//BurstLength
wire[3:
0]cwl=mode_reg2[5:
3]+5;//CASWriteLatency
wire[3:
0]al=(mode_reg1[4:
3]===2'b00)?
4'h0:
cl-mode_reg1[4:
3];//AdditiveLatency
wire[4:
0]rl=cl+al;//ReadLatency
wire[4:
0]wl=cwl+al;//WriteLatency
//dqtransmit
regdq_en;
reg[DM_BITS-1:
0]dm_out;
reg[DQ_BITS-1:
0]dq_out;
regdqs_en;
reg[DQS_BITS-1:
0]dqs_out;
assigndm=dq_en?
dm_out:
{DM_BITS{1'bz}};
assigndq=dq_en?
dq_out:
{DQ_BITS{1'bz}};
assigndqs=dqs_en?
dqs_out:
{DQS_BITS{1'bz}};
assigndqs_n=dqs_en?
~dqs_out:
{DQS_BITS{1'bz}};
//dqreceive
reg[DM_BITS-1:
0]dm_fifo[4*CL_MAX+BL_MAX+2:
0];
reg[DQ_BITS-1:
0]dq_fifo[4*CL_MAX+BL_MAX+2:
0];
wire[DQ_BITS-1:
0]q0,q1,q2,q3;
regptr_rst_n;
reg[1:
0]burst_cntr;
//odt
regodt_out;
reg[(AL_MAX+CL_MAX):
0]odt_fifo;
assignodt=odt_out&!
odt_fifo[0];
//timingdefinitionintCKunits
realtck;
wire[11:
0]tccd=TCCD;
wire[11:
0]tcke=max(ceil(TCKE/tck),TCKE_TCK);
wire[11:
0]tckesr=TCKESR_TCK;
wire[11:
0]tcksre=max(ceil(TCKSRE/tck),TCKSRE_TCK);
wire[11:
0]tcksrx=max(ceil(TCKSRX/tck),TCKSRX_TCK);
wire[11:
0]tcl_min=min_cl(tck);
wire[6:
2]mr_cl=(tcl_min-4)<<2|(tcl_min/12);
wire[11:
0]tcpded=TCPDED;
wire[11:
0]tcwl_min=min_cwl(tck);
wire[5:
3]mr_cwl=tcwl_min-5;
wire[11:
0]tdllk=TDLLK;
wire[11:
0]tfaw=ceil(TFAW/tck);
wire[11:
0]tmod=max(ceil(TMOD/tck),TMOD_TCK);
wire[11:
0]tmrd=TMRD;
wire[11:
0]tras=ceil(TRAS_MIN/tck);
wire[11:
0]trc=ceil(TRC/tck);
wire[11:
0]trcd=ceil(TRCD/tck);
wire[11:
0]trfc=ceil(TRFC_MIN/tck);
wire[11:
0]trp=ceil(TRP/tck);
wire[11:
0]trrd=max(ceil(TRRD/tck),TRRD_TCK);
wire[11:
0]trtp=max(ceil(TRTP/tck),TRTP_TCK);
wire[11:
0]twr=ceil(TWR/tck);
wire[11:
0]twtr=max(ceil(TWTR/tck),TWTR_TCK);
wire[11:
0]txp=max(ceil(TXP/tck),TXP_TCK);
wire[11:
0]txpdll=max(ceil(TXPDLL/tck),TXPDLL_TCK);
wire[11:
0]txpr=max(ceil(TXPR/tck),TXPR_TCK);
wire[11:
0]txs=max(ceil(TXS/tck),TXS_TCK);
wire[11:
0]txsdll=TXSDLL;
wire[11:
0]tzqcs=TZQCS;
wire[11:
0]tzqoper=TZQOPER;
wire[11:
0]wr=(twr<8)?
twr:
twr+twr%2;
wire[11:
9]mr_wr=(twr<8)?
(twr-4):
twr>>1;
`ifdefTRUEBL4
wire[11:
0]tccd_dg=TCCD_DG;
wire[11:
0]trrd_dg=max(ceil(TRRD_DG/tck),TRRD_DG_TCK);
wire[11:
0]twtr_dg=max(ceil(TWTR_DG/tck),TWTR_DG_TCK);
`endif
initialbegin
$timeformat(-9,1,"ns",1);
`ifdefperiod
tck<=`period;
`else
tck<=ceil(TCK_MIN);
`endif
ck<=1'b1;
odt_fifo<=0;
end
//componentinstantiation
ddr3sdramddr3(
rst_n,
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm,
ba,
a,
dq,
dqs,
dqs_n,
tdqs_n,
odt
);
//clockgenerator
always@(posedgeck)begin
ck<=#(tck/2)1'b0;
ck<=#(tck)1'b1;
end
functionintegerceil;
inputnumber;
realnumber;
if(number>$rtoi(number))
ceil=$rtoi(number)+1;
else
ceil=number;
endfunction
functionintegermax;
inputarg1;
inputarg2;
integerarg1;
integerarg2;
if(arg1>arg2)
max=arg1;
else
max=arg2;
endfunction
taskpower_up;
begin
rst_n<=1'b0;
cke<=1'b0;
cs_n<=1'b1;
odt_out<=1'b0;
#(10000);//CKEmustbeLOW10nspriortoRST#transitioningHIGH.
@(negedgeck)rst_n=1'b1;
#(10000)//AfterRST#transitionsHIGH,wait500us(minusoneclock)withCKELOW.(wait10nsinsteadof500us)
@(negedgeck)nop(TXPR/tck+1);//AfterCKEisregisteredHIGHandaftertXPRhasbeensatisfied,MRScommandsmaybeissued.
end
endtask
taskload_mode;
input[BA_BITS-1:
0]bank;
input[ADDR_BITS-1:
0]addr;
begin
case(bank)
0:
mode_reg0=addr;
1:
mode_reg1=addr;
2:
mode_reg2=addr;
endcase
cke<=1'b1;
cs_n<=1'b0;
ras_n<=1'b0;
cas_n<=1'b0;
we_n<=1'b0;
ba<=bank;
a<=addr;
@(negedgeck);
end
endtask
taskrefresh;
begin
cke<=1'b1;
cs_n<=1'b0;
ras_n<=1'b0;
cas_n<=1'b0;
we_n<=1'b1;
@(negedgeck);
end
endtask
taskprecharge;
input[BA_BITS-1:
0]bank;
inputap;//prechargeall
begin
cke<=1'b1;
cs_n<=1'b0;
ras_n<=1'b0;
cas_n<=1'b1;
we_n<=1'b0;
ba<=bank;
a<=(ap<<10);
@(negedgeck);
end
endtask
taskactivate;
input[BA_BITS-1:
0]bank;
input[ROW_BITS-1:
0]row;
begin
cke<=1'b1;
cs_n<=1'b0;
ras_n<=1'b0;
cas_n<=1'b1;
we_n<=1'b1;
ba<=bank;
a<=row;
@(negedgeck);
end
endtask
//writetasksupportsburstlengths<=8
taskwrite;
input[BA_BITS-1:
0]bank;
input[COL_BITS-1:
0]col;
inputap;//AutoPrecharge
inputbc;//BurstChop
input[8*DM_BITS-1:
0]dm;
input[8*DQ_BITS-1:
0]dq;
reg[ADDR_BITS-1:
0]atemp[2:
0];
integeri;
begin
cke<=1'b1;
cs_n<=1'b0;
ras_n<=1'b1;
cas_n<=1'b0;
we_n<=1'b0;
ba<=bank;
atemp[0]=col&10'h3ff;//a[9:
0]=COL[9:
0]
atemp[1]=((col>>10)&1'h1)<<11;//a[11]=COL[10]
atemp[2]=(col>>11)<<13;//a[N:
13]=COL[N:
11]
a<=atemp[0]|atemp[1]|atemp[2]|(ap<<10)|(bc<<12);
casex({bc,mode_reg0[1:
0]})
3'bx00,3'b101:
bl=8;
3'bx1x,3'b001:
bl=4;
endcase
dqs_en<=#(wl*tck-tck/2)1'b1;
dqs_out<=#(wl*tck-tck/2){DQS_BITS{1'b1}};
for(i=0;i<=bl;i=i+1)begin
dqs_en<=#(wl*tck+i*tck/2)1'b1;
if(i%2==0)begin
dqs_out<=#(wl*tck+i*tck/2){DQS_BITS{1'b0}};
endelsebegin
dqs_out<=#(wl*tck+i*tck/2){DQS_BITS{1'b1}};
end
dq_en<=#(wl*tck+i*tck/2+tck/4)1'b1;
dm_out<=#(wl*tck+i*tck/2+tck/4)dm>>i*DM_BITS;
dq_out<=#(wl*tck+i*tck/2+tck/4)dq>>i*DQ_BITS;
end
dqs_en<=#(wl*tck+bl*tck/2+tck/2)1'b0;
dq_en<=#(wl*tck+bl*tck/2+tck/4)1'b0;
@(negedgeck);
end
endtask
//readwithoutdataverification
taskread;
input[BA_BITS-1:
0]bank;
input[COL_BITS-1:
0]col;
inputap;//AutoPrecharge
inputbc;//BurstChop
reg[ADDR_BITS-1:
0]atemp[2:
0];
integeri;
begin
cke<=1'b1;
cs_n<=1'b0;
ras_n<=1'b1;
cas_n<=1'b0;
we_n<=1'b1;
ba<=bank;
atemp[0]=col&10'h3ff;//a[9:
0]=COL[9:
0]
atemp[1]=((col>>10)&1'h1)<<11;//a[11]=COL[10]
atemp[2]=(col>>11)<<13;//a[N:
13]=COL[N:
11]
a<=atemp[0]|atemp[1]|atemp[2]|(ap<<10)|(bc<<12);
casex({bc,mode_reg0[1:
0]})
3'bx00,3'b101:
bl=8;
3'bx1x,3'b001:
bl=4;
endcase
for(i=0;i<(bl/2+2);i=i+1)begin
odt_fifo[rl-wl+i]=1'b1;
end
@(negedgeck);
end
endtask
taskzq_calibration;
inputlong;
begin
cke<=1'b1;
cs_n<=1'b0;
ras_n<=1'b1;
cas_n<=1'b1;
we_n<=1'b0;
ba<=0;
a<=long<<10;
@(negedgeck);
end
endtask
tasknop;
input[31:
0]count;
begin
cke<=1'b1;
cs_n<=1'b0;
ras_n<=1'b1;
cas_n<=1'b1;
we_n<=1'b1;
repeat(count)@(negedgeck);
end
endtask
taskdeselect;
input[31:
0]count;
begin
cke<=1'b1;
cs_n<=1'b1;
ras_n<=1'b1;
cas_n<=1'b1;
we_n<=1'b1;
repeat(count)@(negedgeck);
end
endtask
taskpower_down;
input[31:
0]count;
begin
cke<=1'b0;
cs_n<=1'b1;
ras_n<=1'b1;
cas_n<=1'b1;
we_n<=1'b1;
repeat(count)@(negedgeck);
end
endtask
taskself_refresh;
input[31:
0]count;
begin
cke<=1'b0;
cs_n<=1'b0;
ras_n<=1'b0;
cas_n<=1'b0;
we_n<=1'b1;
cs_n<=#(tck)1'b1;
ras_n<=#(tck)1'b1;
cas_n<=#(tck)1'b1;
we_n<=#(tck)1'b1;
repeat(count)@(negedgeck);
end
endtask
taskpd_change_period;
input[31:
0]new_period;
begin
$display("%mattime%t:
INFO:
ChangingClockPeriodto%08.3fps",$time,new_period);
power_down(tcksre+1);
tck<=new_period;
@(posedgeck);
@(negedgeck);
repeat(tcksrx)@(negedgeck);
end
endtask
tasksr_change_period;
input[31:
0]new_period;
begin
$display("%mattime%t:
INFO:
ChangingClockPeriodto%08.3fps",$time,new_period);
self_refresh(tcksre+1);
tck<=new_period;
@(posedgeck);
@(negedgeck);
repeat(tcksrx)@(negedgeck);
end
endtask
//readwithdataverification
taskread_verify;
input[BA_BITS-1:
0]bank;
input[COL_BITS-1:
0]col;
inputap;//AutoPrecharge
inputbc;//BurstChop
input[8*DM_BITS-1:
0]dm;//ExpectedDataMask
input[8*DQ_BITS-1:
0]dq;//ExpectedData
integeri,j;
begin
read(bank,col,ap,bc);
for(i=0;i j=(col^i)%bl; if(! bo)begin j=(j&-4)+((col+i)&3); end dm_fifo[2*rl+i]=dm>>(i*DM_BITS); dq_fifo[2*rl+i]=dq>>(i*DQ_BITS); end end endtask //receiver(s)fordata_verifyprocess dqrxdqrx[DQS_BITS-1: 0](ptr_rst_n,dqs,dq,q0,q1,q2,q3); //performdataverificationasaresultofread_verifytaskcall always@(ck)begin: data_verify integeri; integerj; reg[DQ_BITS-1: 0]bit_mask; reg[DM_BITS-1: 0]dm_temp; reg[DQ_BITS-1: 0]dq_temp; for(i=! ck;(i<2/(2.0-! ck));i=i+1)begin if(dm_fifo[i]==={DM_BITS{1'bx}})begin burst_cntr=0; endelsebegin dm_temp=dm_fifo[i]; for(j=0;j bit_mask[j]=! dm_te
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