个人作品翻译外文文献电子设计自动化.docx
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个人作品翻译外文文献电子设计自动化.docx
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个人作品翻译外文文献电子设计自动化
附录B翻译原文
Electronicdesignautomation
KeywordEDA;IC;VHDLlanguage;FPGA
PROCESSDESCRIPTION
Threeobstaclesinparticularbedevilicdesignersinthisdawnofthesystemonachip.Thefirstisactuallyashortfall-thehardwareandsoftwarecomponentsofthedesignlackaunifyinglanguage.Then,asthenumberoflogicgatesperchippassesthemillionmarks,verificationofadesign'scorrectnessisfastbecomingmorearduousthandoingthedesignitself.Andfinally,notonlygatecountsbutchipfrequenciesalsoareclimbing,sothatgettingadesigntomeetitstimingrequirementswithouttoomanydesigniterationsisarecedinggoal.
Asisthewontoftheelectronicdesignautomation(EDA)community,theseconcernsarebeingattackedbystart-upcompaniesledbyafewindividualswithbigideasandalittleseedmoney.
PARLEZ-VOUSSUPERLOG?
Asystemonachipcomprisesbothcircuitryandthesoftwarethatrunsonit.Suchadevicemaycontainanembeddedprocessorcorerunningasoftwaremodem.Mostoften,afterthechip'sfunctionalityisspelledout,usuallyonpaper,thehardwarecom-potentishandedofftothecircuitdesignersandthesoftwareisgiventothepro-grammars,tomeetupagainatsomelaterdate.
Thepartofthechipsfunctionalitythatwillendupaslogicgatesandtransistorsiswrit-teninahardwaredesignlanguage-VirologyorVHDL,whilethepartthatwillendupassoftwareismostoftendescribedintheprogramminglanguageCorC++.Theuseofthesedisparatelanguageshamperstheabilitytodescribe,model,anddebugthecircuitryoftheICandthesoftwareinacoherentfashion.
Itistime,manyintheindustrybelieve,foranewdesignlanguagethatcancopewithbothhardwareandsoftwarefromtheinitialdesignspecificationrightthroughtofinalverification.JustsuchanewlanguagehasbeendevelopedbyCo-DesignAutomationInc.,SanJose,Calif.
Beforelaunchingsuchanambitiousenterprise,cofoundersSimonDavidmann,whoisalsochiefoperatingofficer,andPeterFlakeruledouttheusefulnessofextendinganexistinglanguagetomeetsystem-on-chipneeds.AmongthecandidatesforextensionwereC,C++,Java,andVerilog.
Adesignlanguageshouldsatisfythreerequirements,maintainedDavidmann.Itshouldunifythedesignprocess.Itshouldmakedesigningmoreefficient.Anditshouldevolveoutofanexistingmethodology.Noneoftheexistingapproachesfilledthebill.SoDavidmannandFlakesetaboutdevelopingnewco-designlanguagecalledSuperlog.
AnaturalstartingpointwasablendofVirologyandCsince"fromanalgorithmpointofview,alotofVirologyisbuiltonC,"explainedDavidmann.ThentheyspicedtheblendwithbitsandpiecesofVHDLandJava.FromVirologyandVHDL,Superloghasacquiredtheabilitytodescribehardwareaspectsofthedesign,suchassequential,combinatorial,andmultivaluedlogic.FromCandJavaitinheritsdynamicprocessesandothersoftwareconstructs.Evenfunctionslikeinterfaces,protocols,andstatemachines,whichtillnowhaveoftenbeendoneonpaper,canbedescribedinthenewlanguage.Tosupportlegacycodewritteninahardwaredescriptionorprogramminglanguage,SuperlogallowsbothVirologyandCmodulestobeimportedanduseddirectly.
Itisimportantforthelanguagetobeinthepublicdomain,accordingtoDavidmann.Thecompanyhasalreadybeguntoworkwithvariousstandardsorganizationstothisend.
Nottobeoverlookedistheneedforasuiteofdesigntoolsbasedonthelanguage.RecentlyCo-Designidentifiedanumberofelectronicdesignautomationcompanies,amongthemMagmaDesignAutomation,Sente,andViewlogic,thatwilldeveloptoolsbasedonSuperlog.Co-Designwillalsodevelopproductsforthefrontendofthedesignprocess.
ARACETOTHEFINISH
Noteveryoneisconvincedthatanewlanguageisneeded.SystemC,amodelingplatformthatextendsthecapabilitiesandadvantagesofC/C++intothehardwaredomainhasbeenproposedasanalternative.SuchlargeandpowerfulcompaniesasSynopsys,Coware,LucentTechnologies,andTexasInstrumentshavebandedtogetherundertheOpenSystemCInitiativetopromotetheirversionofthenext-generationdesignplatform.TogetSystemCofftoarunningstart,thegroupoffersamodelingplatformfordownloadofftheirWebsitefreeofcharge.Theirhopeisalsotomaketheirplatformthedefactostandard.
TherationalefordevelopingSystemCwasstraightforward,accordingtoJoachimKunkel,generalmanagerandvicepresidentoftheSystemLevelDesignBusinessUnitatSynopsys.Itwastohaveastandardlanguageinwhichsemiconductorvendors,IPvendors,andsystemhousescouldexchangesystem-levelIPandexecutablespecifications,andtheelectronicdesignautomationindustrycoulddevelopinteroperabletools.
SupportersofSystemCbelievethatthewould-bestandardhastobebasedonC++becauseitallowscapabilitiestobeaddedtoitwithoutleavingthelanguagestandard,KunkeltoldJEEESpectrum.MostsoftwaredevelopersuseC++andmanysystemsdevelopersuseC++alreadytodescribetheirsystemsatabehaviorallevel.Buttillnowithasnotbeenpossibletodescribehardwareusingthelanguage.
ThedevelopersofSystemChavesolvedthatproblembydefiningnewC++classlibrariesandasimulationkcrne1thatbringtoC++allofthecapabilitiesneededtodescribehardware."Thesenewclassesimplementnewfunctionality,"explainedKunkel."Forexample,bitvectors-stringsofzerosandones-andalltheoperationsthatyouwoulddoonthem."TheSystemCdevelopersalsoprovidedaclassofsignedandunsignednumbers,thenotionofasignal,andotherconceptsneededtomodelhardware.
Therearestillsomeholes,however.Forexample,itisstillnotpossibletosynthesizeagate-levelnetlistfromaSystcmCdescription.RutsynthesistoolsforSysteniCwouldheanaturalresultofbroadacceptanceofthelanguagewithintheusercommunity,accordingtoKunkel.
ItremainstobeseenwhetherSystemCorSuperlogwinsoutintheend.LeastdesirablewouldbeanoutcomeliketheimpassebetweenVirologyandVHDL,inwhichbothprevailed,forcingelectronicdesignautomationvendorstosupportbothplatformsinawastefulduplicationofeffort.
THEVERIFICATIONNIGHTMARE
Iftoday'scomplexICsaretoughtodesign,theyareverymuchtoughertoverify.Avarietyoftoolsareavailable,eachwithitsprosandcons.Emulationtranslatesadesignintofield-programmablegatearrays(FPGAs).Presumably,ifthearrayworksasplanned,thefinalchipwillalso.Theemulationplatformalsoenablesdesignerstotry0111thesoftwarethatwillrunontheASIC.
Theapproach,though,isslow.Typicalemulationsystemsrunatafewmegahertz."Atroughlyonemillioncyclespersecond,designersarcnotgettingcnoughperformanceoutoftheiremulationsystemstoverifyorunderstandsomeofthethingsthataregoingonwithvideogenerationorhighbandwidthcommunications,"saidJohnGallagher,directorofmarketingforSynplicityInc.,Sunnyvale,Calif.Theymustprocessalargenumberofoperationstoensuretheirfunctionalityiscorrect,headded.
Thereasonthatemulationsystemsaresoslow,accordingtoGallagher,isthattheyroutethedesignthroughmanyFPGAsandmanyboards.Simplicitysolutionistouseafewhigh-endFPGAshavingoveronemilliongatesrunningat100MHz.Typically,amillionFPGAgatestranslatesinto200000ASICgates.Puttingninesuchchipsonaboardinathree-by-threearrayallowsdesignerstorepresentupto1.8millionASlCgates.Androutingdelaysaregreatlycurtailedbecauseeachchipisnomorethantwohopsawayfromanyotherchipinthearray.
Thecompany%product,calledCertify,isnotintendedtocompetewithreconfigurableemulationsystems,whichareveryeffectiveatdebuggingdesignsduringtheinternaldesignprocess,explainedGallagher.Rather,itisatrueprototypeofthesystem,runningatspeedsthatmayapproachtherealthing.
Certifyhandlesthreefundamentaloperations,saidGallagher.Thefirstispartitioning,orbreakingsuptheASICregistertransferlevel(RTL)codeintodifferentFPGAs.Itdoessynthesis,turningtheRTLcodeintoASICgatesequivalenttothefinalASICgates.Thenitdoestiminganalysis."Wehaven'tjustlinkedtogetherthedifferenttools,”heexplained.'Wehavetakaoursynthesisalgorithms,betweenthepartitioningcapabilities,andlaidthetiminganalysisacrossthat."
Inadditiontoemulation,twocomplementaryapproachestodesignverificationaresimulationandmodelchecking,atypeofformalverification.Simulationappliesvectorstoasoftwaremodelofadesignandcheckstoseciftheoutputhasthecorrectvalue.Theapproachisstraightforward,butisbecomingincreasinglytortuousasdesignsbecomemorecomplicatedandthenumberofpossibletestvectorsmushrooms.Sorecently,electronicdesignautomationcompanieshavebeenturningtomodelcheckingtoprovethatdesignsarecorrectlydone.
Thestickingpointwithmodelcheckingisitsgreatdifficultyofuse."Itisnotformostengineers,"saidSimonNapper,chiefoperatingofficerOFInnol-ogicSystemsInc.,SanJose,Calif."Theusagemodelisverydifficult-itchecksproperties.Butthedesignerisn'tfamiliarwithwhatPpropertyis-heisusedtosimulationandstatictiming."
Asaremedy,InnoLogicdevelopedasymbolicsimulationtool,whichblendssimulationandformalverification.ItisaVirologysimulatorexceptinsteadofsendingIsandOsthroughthelogic,thetoo1propagatessymbolorsymbolsplusbinaryvalues.Theusergainsimprovedfunctionalcoveragedongwithmuchfasterverification.
Toillustrate,tocompletelyverifyafourbitadderwouldrequire256binaryvectors-andtake256simulationcycles.Wit
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