EDA基于VHDL的电子密码锁设计报告.docx
- 文档编号:18567406
- 上传时间:2023-08-19
- 格式:DOCX
- 页数:25
- 大小:181.06KB
EDA基于VHDL的电子密码锁设计报告.docx
《EDA基于VHDL的电子密码锁设计报告.docx》由会员分享,可在线阅读,更多相关《EDA基于VHDL的电子密码锁设计报告.docx(25页珍藏版)》请在冰点文库上搜索。
EDA基于VHDL的电子密码锁设计报告
密码锁设计
密码锁设计顶层电路图
(2)顶层时序仿真
分频模块
(1)10分频程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_div10is
port(clk:
instd_logic;
co:
outstd_logic);
end;
architecturebehavofyourname_div10is
signalcount:
std_logic_vector(3downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'then
ifcount="1001"then
count<="0000";
co<='1';
else
count<=count+1;
co<='0';
endif;
endif;
endprocess;
endbehav;
(2)5分频程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_div5is
port(clk:
instd_logic;
co:
outstd_logic);
end;
architecturebehavofyourname_div5is
signalcount:
std_logic_vector(2downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'then
ifcount="100"then
count<="000";
co<='1';
else
count<=count+1;
co<='0';
endif;
endif;
endprocess;
endbehav;
(3)10分频时序仿真波形
(4)5分频时序仿真波形
从以上波形仿真可以看出该板块10分频模块的输出是输入信号的10分频,同理5分频的输出是输入信号的5分频。
附录三:
消抖模块
(1)消抖模块程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_xiaodouis
port(clk_1k:
instd_logic;
keyin:
instd_logic;
keyout:
outstd_logic);
end;
architecturebehavofyourname_xiaodouis
signaln:
integerrange0to29;
begin
process(clk_1k)
begin
ifkeyin='1'then
n<=0;
keyout<='1';
elsifclk_1k'eventandclk_1k='1'then
ifn<29then
n<=n+1;
keyout<='1';
else
n<=29;
keyout<='0';
endif;
endif;
endprocess;
endbehav;
(2)仿真波形
附录四:
输入模块
(1)输入模块程序
1.yourname_count10模块程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_count10is
port(clk:
instd_logic;
bcd:
bufferstd_logic_vector(3downto0));
end;
architecturebehavofyourname_count10is
begin
process(clk)
begin
ifclk'eventandclk='1'then
ifbcd="1001"then
bcd<="0000";
else
bcd<=bcd+'1';
endif;
endif;
endprocess;
endbehav;
2.yourname_kaiqi模块程序
libraryieee;
useieee.std_logic_1164.all;
entityyourname_kaiqiis
port(clk:
instd_logic;
sel:
instd_logic;
input:
instd_logic_vector(3downto0);
output:
outstd_logic_vector(3downto0));
end;
architecturebehavofyourname_kaiqiis
begin
process(clk,sel)
begin
ifsel='1'then
output<=input;
elseoutput<="0000";
endif;
endprocess;
endbehav;
3.yourname_input模块程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityyourname_inputis
port(sure:
instd_logic;
sel:
instd_logic;
bcd:
instd_logic_vector(3downto0);
input1:
outstd_logic_vector(3downto0);
input2:
outstd_logic_vector(3downto0);
input3:
outstd_logic_vector(3downto0);
input4:
outstd_logic_vector(3downto0));
end;
architecturebehavofyourname_inputis
signalq:
std_logic_vector(23downto0);
begin
process(sure,sel,q)
begin
ifsel='1'then
q(3downto0)<=bcd;
ifsure='1'andsure'eventthen
q(7downto4)<=q(3downto0);
q(11downto8)<=q(7downto4);
q(15downto12)<=q(11downto8);
endif;
elsifsel='0'then
q(3downto0)<="0000";
q(7downto4)<="0000";
q(11downto8)<="0000";
q(15downto12)<="0000";
endif;
endprocess;
input1<=q(3downto0);
input2<=q(7downto4);
input3<=q(11downto8);
input4<=q(15downto12);
endbehav;
(2)输入模块图
(3)输入模块时序仿真波形图
由以上仿真结果可以看出,每一个input脉冲,都使a计数,每个sure脉冲让a的计数移位到b,b的数值移位到下一位。
而open和sel一直要保持高有效。
附录五:
预置密码模块
1.yourname_set模块程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityyourname_setis
port(clk:
instd_logic;
reset:
instd_logic;
sel:
instd_logic;
input1:
instd_logic_vector(3downto0);
input2:
instd_logic_vector(3downto0);
input3:
instd_logic_vector(3downto0);
input4:
instd_logic_vector(3downto0);
pass1:
outstd_logic_vector(3downto0);
pass2:
outstd_logic_vector(3downto0);
pass3:
outstd_logic_vector(3downto0);
pass4:
outstd_logic_vector(3downto0));
end;
architecturebehavofyourname_setis
signalq1:
std_logic_vector(3downto0):
="0100";
signalq2:
std_logic_vector(3downto0):
="0111";
signalq3:
std_logic_vector(3downto0):
="0011";
signalq4:
std_logic_vector(3downto0):
="1000";
begin
process(clk,reset)
begin
ifclk='1'andclk'eventthen
ifreset='1'andsel='1'then
q1<=input1;
q2<=input2;
q3<=input3;
q4<=input4;
elsenull;
endif;
endif;
endprocess;
pass1<=q1;
pass2<=q2;
pass3<=q3;
pass4<=q4;
endbehav;
2.yourname_cunma模块程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityyourname_cunmais
port(a:
instd_logic_vector(3downto0);
b:
instd_logic_vector(3downto0);
c:
instd_logic_vector(3downto0);
d:
instd_logic_vector(3downto0);
pass1:
outstd_logic_vector(3downto0);
pass2:
outstd_logic_vector(3downto0);
pass3:
outstd_logic_vector(3downto0);
pass4:
outstd_logic_vector(3downto0);
reset:
instd_logic;
clk:
instd_logic);
end;
architecturecunma_behaveofyourname_cunmais
signalq1:
std_logic_vector(3downto0);
signalq2:
std_logic_vector(3downto0);
signalq3:
std_logic_vector(3downto0);
signalq4:
std_logic_vector(3downto0);
begin
process(reset,clk)
begin
ifclk='1'andclk'eventthen
ifreset='1'then
q1<=a;
q2<=b;
q3<=c;
q4<=d;
elsifreset='0'then
pass1<=q1;
pass2<=q2;
pass3<=q3;
pass4<=q4;
elsenull;
endif;
endif;
endprocess;
endcunma_behave;
(2)预置密码模块电路
(3)预置密码模块时序仿真波形
从以上仿真结果可以看出,当reset给一个开启—关闭的脉冲信号时,初始密码被传递到输出端,当reset和sel都有效时,输入端重置的密码被传递到输出端,逻辑结果符合设计要求。
附录六:
密码比较模块
yourname_match模块程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityyourname_matchis
port(clk:
instd_logic;
check:
instd_logic;
input1:
instd_logic_vector(3downto0);
input2:
instd_logic_vector(3downto0);
input3:
instd_logic_vector(3downto0);
input4:
instd_logic_vector(3downto0);
pass1:
instd_logic_vector(3downto0);
pass2:
instd_logic_vector(3downto0);
pass3:
instd_logic_vector(3downto0);
pass4:
instd_logic_vector(3downto0);
result:
outstd_logic);
end;
architecturebehavofyourname_matchis
signali:
std_logic_vector(15downto0);
signalp:
std_logic_vector(15downto0);
signalq:
std_logic:
='0';
begin
i<=input4&input3&input2&input1;
p<=pass4&pass3&pass2&pass1;
process(clk,check)
begin
ifclk='1'andclk'eventthen
ifcheck='0'then
ifi=pthen
q<='1';
else
q<='0';
endif;
endif;
endif;
endprocess;
result<=q;
endbehav;
(2)密码比较模块电路图
(3)密码比较模块时序仿真波形
从以上波形可以看出,当checka按键有效时,i与p端密码相同时result为高,相异时为低,逻辑符合设计要求。
附录七:
密码比较显示模块1.yourname_ring模块程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityyourname_ringis
port(clk1kHz:
instd_logic;
check:
instd_logic;
result:
instd_logic;
sel:
instd_logic;
led:
outstd_logic);
end;
architecturebehavofyourname_ringis
signall:
std_logic;
begin
process(clk1kHz,result)
begin
ifsel='0'then
l<='0';
elsifresult='0'andcheck='0'then
l<='1';
elsenull;
endif;
endprocess;
led<=l;
endbehav;
2.yourname_kaisuo模块程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityyourname_kaisuois
port(clk:
instd_logic;
sel:
instd_logic;
check:
instd_logic;
opeh:
instd_logic;
lock:
outstd_logic);
end;
architecturebehavofyourname_kaisuois
signalq:
std_logic;
begin
process(clk)
begin
ifsel='0'then
q<='0';
elsifopeh='1'andcheck='0'then
q<='1';
elsenull;
endif;
endprocess;
lock<=q;
endbehav;
(2)kaisuo时序仿真波形图
从以上仿真可以看出,checka按键有效时,当opeh即比较结果为低时,q输出未知,当比较结果为高时,q输出结果为高,符合设计逻辑。
(3)ring时序仿真图形
从以上仿真波形可以看出,在checka按键有效时,当比较结果result为低时,输出为高,当比较结果为高时,输出为低,符合设计逻辑。
附录八:
七段显示模块
1.yourname_xianshi0模块程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityyourname_xianshi0is
port(sel:
instd_logic;
clk:
instd_logic;
din1:
instd_logic_vector(3downto0);
din2:
instd_logic_vector(3downto0);
din3:
instd_logic_vector(3downto0);
din4:
instd_logic_vector(3downto0);
dout1:
outstd_logic_vector(3downto0);
dout2:
outstd_logic_vector(3downto0);
dout3:
outstd_logic_vector(3downto0);
dout4:
outstd_logic_vector(3downto0));
end;
architecturebehavofyourname_xianshi0is
begin
process(clk)
begin
ifclk'eventandclk='1'then
ifsel='0'then
dout1<="0000";
dout2<="0000";
dout3<="0000";
dout4<="0000";
else
dout1<=din1;
dout2<=din2;
dout3<=din3;
dout4<=din4;
endif;
endif;
endprocess;
endbehav;
2.yourname_xianshi模块程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyourname_xianshiis
port(din0:
instd_logic_vector(3downto0);
din1:
instd_logic_vector(3downto0);
din2:
instd_logic_vector(3downto0);
din3:
instd_logic_vector(3downto0);
clk:
instd_logic;
led_sa:
outstd_logic;
led_sb:
outstd_logic;
led_sc:
outstd_logic;
led_a:
outstd_logic;
led_b:
outstd_logic;
led_c:
outstd_logic;
led_d:
outstd_logic;
led_e:
outstd_logic;
led_f:
outstd_logic;
led_g:
outstd_logic;
led_dp:
outstd_logic);
end;
architecturebehavofyourname_xianshiis
signalseg:
std_logic_vector(6downto0);
signalnum:
std_logic_vector(3downto0);
signals:
std_logic_vector(2downto0);
signalsel:
std_logic_vector(2downto0);
begin
led_sa<=sel(0);
led_sb<=sel
(1);
led_sc<=sel
(2);
led_a<=seg(0);
led_b<=seg
(1);
led_c<=seg
(2);
led_d<=seg(3);
led_e<=seg(4);
led_f<=seg(5);
led_g<=seg(6);
process(clk)
begin
ifclk'eventandclk='1'
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- EDA 基于 VHDL 电子 密码锁 设计 报告