AT89S52技术手册.docx
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AT89S52技术手册.docx
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AT89S52技术手册
AT89S52
Features
•CompatiblewithMCS-51®Products
•8KBytesofIn-SystemProgrammable(ISP)FlashMemory
•1000Write/EraseCycles
•FullyStaticOperation:
0Hzto33MHz
•Three-levelProgramMemoryLock
•256x8-bitInternalRAM
•32ProgrammableI/OLines
•Three16-bitTimer/Counters
•EightInterruptSources
•FullDuplexUARTSerialChannel
•Low-powerIdleandPower-downModes
•InterruptRecoveryfromPower-downMode
•WatchdogTimer
•DualDataPointer
•Power-offFlag
Description
TheAT89S52isalow-power,high-performanceCMOS8-bitmicrocontrollerwith8Kbytesofin-systemprogrammableFlashmemory.ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithinsystemprogrammableFlashonamonolithicchip,theAtmelAT89S52isapowerfulicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheAT89S52providesthefollowingtandardfeatures:
8KbytesofFlash,256bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,three16-bittimer/counters,asix-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextinterruptorhardwarereset.
PinConfigurations
BlockDiagram
PinDescription
VCC
Supplyvoltage.
GND
Ground.
Port0
Port0isan8-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceInputs.
Port0canalsobeconfiguredtobethemultiplexedloworderaddress/databusduringccessestoexternalprogramanddatamemory.Inthismode,P0hasint-ernalpullups.
Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesdur-ingprogramverification.Externalpullupsarerequiredduringprogramveri-fication.
Port1
Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.
Inaddition,P1.0andP1.1canbeconfiguredtobetheti-mer/counter2exte-rnalcountinput(P1.0/T2)andthetimer/counter2triggerinput(P1.1/T2EX),respectively,asshowninthefollowingtable.
Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
PortPin
AlternateFunctions
P1.0
T2(externalcountinputtoTimer/Counter2),clock-out
P1.1
T2EX(Timer/Counter2capture/reloadtriggeranddirectioncontrol)
P1.5
MOSI(usedforIn-SystemProgramming)
P1.6
MISO(usedforIn-SystemProgramming)
P1.7
SCK(usedforIn-SystemProgramming)
Port2
Port2isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.
Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpullupswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.
Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.
Port3
Port3isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,
Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepullups.
Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S52,asshowninthefollowingtable.
Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.
PortPin
AlternateFunctions
P3.0
RXD(serialinputport)
P3.1
TXD(serialoutputport)
P3.2
(externalinterrupt0)
P3.3
(externalinterrupt1)
P3.4
T0(timer0externalinput)
P3.5
T1(timer1externalinput)
P3.6
(externaldatamemorywritestrobe)
P3.7
(externaldatamemoryreadstrobe)
RST
Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.ThispindrivesHighfor96oscillatorperiodsaftertheWatchdogtimesout.TheDISRTObitinSFRAUXR(address8EH)canbeusedtodisablethisfeature.InthedefaultstateofbitDISRTO,theRESETHIGHoutfeature
isenabled.
ALE/
AddressLatchEnable(ALE)isanoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(
)duringFlashprogramming.
Innormaloperation,ALEisemittedataconstantrateof1/6theoscillatorfrequ-encyandmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternaldatamemory.
Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicroco-ntrollerisinexternalexecutionmode.
ProgramStoreEnable(
)isthereadstrobetoexternalprogrammemory.
WhentheAT89S52isexecutingcodefromexternalprogrammemory,
isactivatedtwiceeachmachinecycle,exceptthattwo
activationsareskippedduringeachaccesstoexternaldatamemory.
/VPP
ExternalAccessEnable.
mustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,
willbeternallylatchedonreset.
shouldbestrappedtoVCCforinternalrogramexecutions.Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming.
XTAL1
Inputtotheinvertingoscillatoramplifierandinputtothenternalclockoperatingcircuit.
XTAL2
Outputfromtheinvertingoscillatoramplifier.
SpecialFunctionRegisters
Amapoftheon-chipmemoryareacalledtheSpecialFunctionRegister(SFR)spaceisshowninTable1.Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.
Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfeatures.Inthatcase,theresetornactivevaluesofthenewbitswillalwaysbe0.
Timer2Registers:
ControlandstatusbitsarecontainedinregistersT2CON(showninTable2)andT2MOD(showninTable3)forTimer2.Theregisterpair(RCAP2H,RCAP2L)aretheCapture/ReloadregistersforTimer2in16-bitcapturemodeor16-bitauto-reloadmode.
InterruptRegisters:
TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthesixinterruptsourcesintheIPregister.
Timer2OperatingModes
RCLK+TCLK
CP/RL2
TR2
MODE
0
0
1
16-bitAuto-reload
0
1
1
16-bitCapture
1
×
1
BaudRateGenerator
×
×
0
(Off)
IntheCounterfunction,theregisterisincrementedinresponsetoa1-to-0transitionatitscorrespondingexternalinputpin,T2.Inthisfunction,theexternalinputissampledduringS5P2ofeverymachinecycle.Whenthesamplesshowahighinonecycleandalowinthenextcycle,thecountisincremented.ThenewcountvalueappearsintheregisterduringS3P1ofthecyclefollowingtheoneinwhichthetransitionwasdetected.Sincetwomachinecycles(24oscillatorperiods)arerequiredtorecognizea1-to-0transition,themaximumcountrateis1/24oftheoscillatorfrequency.Tonsurethatagivenlevelissampledatleastoncebeforeitchanges,thelevelshouldbeheldforatleastonefullmachinecycle.
Interrupts
TheAT89S52hasatotalofsixinterruptvectors:
twoexternalinterrupts(INT0andINT1),threetimerinterrupts(Timers0,1,and2),andtheserialportinterrupt.TheseinterruptsareallshowninFigure10.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunctionRegisterIE.IEalsocontainsaglobaldisablebit,EA,which
disablesallinterruptsatonce.NotethatTable5showsthatbitpositionIE.6isunimplemented.IntheAT89S52,bitpositionIE.5isalsounimplemented.
Usersoftwareshouldnotwrite1stothesebitpositions,sincetheymaybeusedinfutureAT89products.Timer2interruptisgeneratedbythelogicalORofbitsTF2andEXF2inregisterT2CON.Neitheroftheseflagsisclearedbyhardwarewhentheserviceroutineisvectoredto.Infact,theserviceroutinemayhavetodeterminewhetheritwasTF2orEXF2thatgeneratedtheinterrupt,andthatbitwillhave
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