可编程逻辑器件的实验程序.docx
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- 上传时间:2023-07-12
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可编程逻辑器件的实验程序.docx
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可编程逻辑器件的实验程序
LS04非门
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYFM04IS
PORT(A:
INSTD_LOGIC;
Y:
OUTSTD_LOGIC);
END;
ARCHITECTUREbhvOFFM04IS
BEGIN
PROCESS(A)
BEGIN
IFA='1'THENY<='0';
ELSEY<='1';
ENDIF;
ENDPROCESS;
ENDARCHITECTUREbhv;
LS08与门
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYYM08IS
PORT(A,B:
INBIT;
Y:
OUTBIT);
ENDENTITYYM08;
ARCHITECTUREoneOFYM08IS
BEGIN
PROCESS(A,B)
BEGIN
IFA='1'ANDB='1'THENY<='1';
ELSEY<='0';
ENDIF;
ENDPROCESS;
ENDARCHITECTUREone;
LS10与非门
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYYF10IS
PORT(A,B,C:
INBIT;
Y:
OUTBIT);
ENDENTITYYF10;
ARCHITECTUREoneOFYF10IS
BEGIN
PROCESS(A,B,C)
BEGIN
IFA='1'ANDB='1'ANDC='1'THENY<='0';
ELSEY<='1';
ENDIF;
ENDPROCESS;
ENDARCHITECTUREone;
LS32或门
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYHM32IS
PORT(A,B:
INBIT;
Y:
OUTBIT);
ENDENTITYHM32;
ARCHITECTUREoneOFHM32IS
BEGIN
PROCESS(A,B)
BEGIN
IFA='0'ANDB='0'THENY<='0';
ELSEY<='1';
ENDIF;
ENDPROCESS;
ENDARCHITECTUREone;
LS49数码管驱动器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYLS49IS
PORT(CLK:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDLS49;
ARCHITECTUREBHVOFLS49IS
SIGNALQ1:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFQ1="1001"
THENQ1<="0000";
ELSE
Q1<=Q1+1;
ENDIF;
ENDIF;
Q<=Q1;
ENDPROCESS;
ENDBHV;
LS74零和预置功能的双正边沿触发的D类触发器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYLS74IS
PORT(CLK,D,CLR,PR:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC);
ENDLS74;
ARCHITECTUREKOIOFLS74IS
SIGNALQ1:
STD_LOGIC;
BEGIN
PROCESS(CLK,CLR,PR)
BEGIN
IF(CLK'EVENTANDCLK='1'ANDCLR='1'ANDPR='1')THEN
Q1<=D;
IF(CLR='1'ANDPR='0')THEN
Q1<='1';
ELSIF(CLR='0'ANDPR='1')THEN
Q1<='0';
ELSIF(CLR='0'ANDPR='0')THEN
Q1<=NULL;--1
ELSIF(CLK='0')THEN
Q1<=Q1;--2
ENDIF;
ENDIF;
Q<=Q1;
ENDPROCESS;
ENDKOI;
LS86与或非门
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYYHM86IS
PORT(A,B:
INBIT;
Y:
OUTBIT);
ENDENTITYYHM86;
ARCHITECTUREoneOFYHM86IS
BEGIN
PROCESS(A,B)
BEGIN
IFA=BTHENY<='0';
ELSEY<='1';
ENDIF;
ENDPROCESS;
ENDARCHITECTUREone;
LS138三线-八线译码器
libraryieee;
useieee.std_logic_1164.all;
entityls138is
port(g1,g2,a,b,c:
instd_logic;
y:
outstd_logic_vector(7downto0));
endls138;
architecturekoiofls138is
signalabc:
std_logic_vector(2downto0);
begin
abc=a&b&c;
process(g1,g2,abc)
begin
if(g1='1'andg2='0')then
caseabcis
when"000"=>y<="11111110";
when"001"=>y<="11111101";
when"010"=>y<="11111011";
when"011"=>y<="11110111";
when"100"=>y<="11101111";
when"101"=>y<="11011111";
when"110"=>y<="10111111";
when"111"=>y<="01111111";
whenothers=>y<="XXXXXXXX";
enscase;
else
y<="11111111";
endif;
endprocess;
endkoi;
LS14510位集电极开路译码器/驱动器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYLS145IS
PORT(EN:
INSTD_LOGIC;
INPUTS:
INSTD_LOGIC_VECTOR(3DOWNTO0);
OUTPUTS:
OUTSTD_LOGIC_VECTOR(9DOWNTO0)
);
END;
ARCHITECTUREKOIOFLS145IS
SIGNALSEL:
STD_LOGIC_VECTOR(4DOWNTO0);
BEGIN
PROCESS(EN,INPUTS)
BEGIN
SEL<=EN&INPUTS;
CASESELIS
WHEN"00000"=>OUTPUTS<="0111111111";
WHEN"00001"=>OUTPUTS<="1011111111";
WHEN"00010"=>OUTPUTS<="1101111111";
WHEN"00011"=>OUTPUTS<="1110111111";
WHEN"00100"=>OUTPUTS<="1111011111";
WHEN"00101"=>OUTPUTS<="1111101111";
WHEN"00110"=>OUTPUTS<="1111110111";
WHEN"00111"=>OUTPUTS<="1111111011";
WHEN"01000"=>OUTPUTS<="1111111101";
WHEN"01001"=>OUTPUTS<="1111111110";
WHENOTHERS=>OUTPUTS<="1111111111";
ENDCASE;
ENDPROCESS;
ENDKOI;
LS157四2选1数据选择器
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYls157IS
PORT
(
a:
INSTD_LOGIC_VECTOR(3DOWNTO0);
b:
INSTD_LOGIC_VECTOR(3DOWNTO0);
g:
instd_logic;
ab:
instd_logic;
y:
OUTSTD_LOGIC_VECTOR(3DOWNTO0)
);
END;
ARCHITECTUREONEOFls157IS
BEGIN
PROCESS(a,b,ab,g)
BEGIN
ifg='1'theny<="0000";
elsifab='0'theny<=a;
elsey<=b;
endif;
ENDPROCESS;
END;
LS1668位移位寄存器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYls166IS
PORT(CLR,SL,clkinh,CLK,SER:
INSTD_LOGIC;
ha:
INSTD_LOGIC_VECTOR(7DOWNTO0);
QH:
OUTSTD_LOGIC);
END;
ARCHITECTUREBEHAVOFls166IS
SIGNALTMPREG8:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
PROCESS(CLK,SL,clkinh,CLR)
begin
IF(CLR='0')THEN
TMPREG8<="00000000";
ELSIF(CLK'EVENT)AND(CLK='1')AND(clkinh='0')THEN
IF(SL='0')THEN
TMPREG8<=ha;
ELSIF(SL='1')THEN
FORIIN7DOWNTO1LOOP
TMPREG8(I)<=TMPREG8(I-1);
ENDLOOP;
TMPREG8(0)<=SER;
ENDIF;
ENDIF;
ENDPROCESS;
Qh<=TMPREG8(7);
ENDBEHAV;
LS240
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYLS240IS
PORT(G1,G2:
INSTD_LOGIC;
A1,A2:
INSTD_LOGIC_VECTOR(3DOWNTO0);
OUTY1,OUTY2:
OUTSTD_LOGIC_VECTOR(3DOWNTO0)
);
END;
ARCHITECTUREKOIOFLS240IS
SIGNALY1,Y2:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
OU1:
PROCESS(G1,A1)
BEGIN
IFG1='0'THENY1<=NOTA1;
ELSEY1<="ZZZZ";
ENDIF;
ENDPROCESSOU1;
OU2:
PROCESS(G2,A2)
BEGIN
IFG2='0'THENY2<=NOTA2;
ELSEY2<="ZZZZ";
ENDIF;
ENDPROCESSOU2;
OUTY1<=Y1;
OUTY2<=Y2;
END;
LS1442组4输入三态缓冲接收器
libraryieee;
useieee.std_logic_1164.all;
entityls244is
port(oc:
instd_logic;
a:
instd_logic_vector(3downto0);
y:
outstd_logic_vector(3downto0);
end;
architectureoneofls244is
begin
process(a,oc)
begin
ifoc='0'then
y<=a;
elsifoc='1'then
y<="ZZZZZZZZ";
endprocess;
end;
LS245三态输出的八组总线收发器
libraryieee;
useieee.std_logic_1164.all;
entityls245is
port(oe,dir:
instd_logic;
a,b:
inoutstd_logic_vector(7downto0));
endls245;
architecturekoiofls245is
signalaout,bout:
std_logic_vector(7downto0);
begin
ou1:
process(oe,dir,b)
begin
if(oe='0'anddir='0')then
aout<=b;
elseaout<="ZZZZZZZZ";
endif;
a<=aout;
endprocessou1;
ou2:
process(oe,dir,a)
begin
if(oe='0'anddir='1')then
bout<=a;
elsebout<="ZZZZZZZZ";
endif;
b<=bout;
endprocessou2;
endkoi;
LS373三态输出的八D触发器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYLS373IS
PORT(C,OC:
INSTD_LOGIC;
D:
INSTD_LOGIC_VECTOR(7DOWNTO0);
Q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
END;
ARCHITECTUREKOIOFLS373IS
SIGNALOUTY:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
PROCESS(C,OC,D)
BEGIN
IFOC='0'THEN
IFC='1'THEN
OUTY<=D;
ENDIF;
ELSEOUTY<="ZZZZZZZZ";
ENDIF;
ENDPROCESS;
Q<=OUTY;
ENDKOI;
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