硬件结构设计.docx
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硬件结构设计.docx
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硬件结构设计
摘要:
本次实验的功能是进行两个4位数的加法运算,并进行结果输出。
在本次实验中,我们用到data_bus作为总线进行传输,reg_74373作为寄存器进行数据的存储,alu_74181进行加法运算。
romc作为译码器进行初始状态的设定。
通过这个加法器的设计,能够对硬件结构设计有了更好的了解,同时也加深了对计算机组成原理课程的理解。
硬件结构设计原理:
1.把模块romc改为九位输出oen,we1,we2,gwe1,oen_n1,gwe2,
oen_n2,gwe3,oen_n3;
2.把模块reg_74244改为四位输入Din(30)和四位输出Qout(30);3.把模块data_bus改为四位输入data_in1(30),Data_in2(30),四位输出data_out1(30),data_out2(30),data_out3(30);
4.把模块reg_74373改为四位输入Din(30)和四位输出Qout(30);5.把模块alu_74181改为四位输入A(30),B(30),S(30),和四位输出F(30)
6.由romc向reg_74244中分别输入两个四位二进制的数,通过九位romc微程序控制器,在进入data_bus后,两个数分别被写入两个reg_74373中,再进入alu_74181进行加法运算,将运算结果输入data_bus,再由另外一个reg_74373读出。
原理图:
管脚图:
###------------CLOCK-----------
NET"clk"LOC="L15";
###-------------Atlysledoutput-------------------
#NET"atlys_led[0]"LOC=U18;#AtlysLD0
#NET"atlys_led[1]"LOC=M14;#AtlysLD1
#NET"atlys_led[2]"LOC=N14;#AtlysLD2
#NET"atlys_led[3]"LOC=L14;#AtlysLD3
#NET"atlys_led[4]"LOC=M13;#AtlysLD4
#NET"atlys_led[5]"LOC=D4;#AtlysLD5
#NET"atlys_led[6]"LOC=P16;#AtlysLD6
#NET"atlys_led[7]"LOC=N12;#AtlysLD7
###-----------AtlysSwitchinput-------------------
#NET"atlys_sw[0]"LOC=A10;#Atlyssw0
#NET"atlys_sw[1]"LOC=D14;#Atlyssw1
#NET"atlys_sw[2]"LOC=C14;#Atlyssw2
#NET"atlys_sw[3]"LOC=P15;#Atlyssw3
#NET"atlys_sw[4]"LOC=P12;#Atlyssw4
#NET"atlys_sw[5]"LOC=R5;#Atlyssw5
#NET"atlys_sw[6]"LOC=T5;#Atlyssw6
#NET"atlys_sw[7]"LOC=E4;#Atlyssw7
###------------EES261switchinput----------
NET"din[0]"LOC="U11";#SW20
NET"din[1]"LOC="R10";#SW19
NET"din[2]"LOC="U10";#SW18
NET"din[3]"LOC="R8";#SW17
NET"S[0]"LOC="M8";#SW16
NET"S[1]"LOC="U8";#SW15
NET"S[2]"LOC="U7";#SW14
NET"S[3]"LOC="N7";#SW13
#NET"C_n"LOC="T6";#SW12
#NET"C_n_Plus"LOC="R7";#SW11
#NET"XLXN_9"LOC="N6";#SW10
#NET"swt[8]"LOC="U5";#SW9
#NET"swt[7]"LOC="V5";#SW8
#NET"swt[6]"LOC="P7";#SW7
#NET"swt[5]"LOC="T7";#SW6
#NET"swt[4]"LOC="V6";#SW5
NET"s0"LOC="P8";#SW4
NET"s1"LOC="V7";#SW3
NET"s2"LOC="V8";#SW2
NET"s3"LOC="N8";#SW1
##----------EES261ledsoutput------------
NET"XLXN_21<0>"LOC="U16";#LED1
NET"XLXN_21<1>"LOC="U15";#LED2
NET"XLXN_21<2>"LOC="U13";#LED3
NET"XLXN_21<3>"LOC="M11";#LED4
NET"XLXN_9"LOC="R11";#LED5
#NET"led<5>"LOC="T12";#LED6
#NET"led<6>"LOC="N10";#LED7
#NET"led<7>"LOC="M10";#LED8
###-------hex7seg-------------------
#NET"an<0>"LOC="V16";
#NET"an<1>"LOC="V15";
#NET"an<2>"LOC="V13";
#NET"an<3>"LOC="N11";
#NET"a_to_g<0>"LOC="T8";#a
#NET"a_to_g<1>"LOC="V10";#b
#NET"a_to_g<2>"LOC="T10";#c
#NET"a_to_g<3>"LOC="V11";#d
#NET"a_to_g<4>"LOC="N9";#e
#NET"a_to_g<5>"LOC="P11";#f
#NET"a_to_g<6>"LOC="V12";#g
#NET"dp"LOC="T11";#dp
###--------------END---------
微程序控制操作方法:
s0s1s2s3oenwe1we2gwe1oen_n1gwe2oen_n2gwe3oen_n3
0000100010101
0001010010101
0011010110101
0010010011001
0110010000001
0100000010101
0101001010101
0111001010111
1000001010110
微程序:
Romc改编代码
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useieee.std_logic_unsigned.all;
entityromcis
Port(s0:
inSTD_LOGIC;
s1:
inSTD_LOGIC;
s2:
inSTD_LOGIC;
s3:
inSTD_LOGIC;
oen:
outSTD_LOGIC;
we1:
outSTD_LOGIC;
we2:
outSTD_LOGIC;
gwe1:
outSTD_LOGIC;
oen_n1:
outSTD_LOGIC;
gwe2:
outSTD_LOGIC;
oen_n2:
outSTD_LOGIC;
gwe3:
outSTD_LOGIC;
oen_n3:
outSTD_LOGIC
);
endromc;
architectureBehavioralofromcis
signaladdr:
std_logic_vector(1downto0);--input
signalrdata:
std_logic_vector(3downto0);--output
begin
addr<=s3&s2&s1&s0;
process(addr)
begin
case(addr)is
when"0000"=>rdata<="100010101";
when"0001"=>rdata<="010010101";
when"0011"=>rdata<="010110101";
when"0010"=>rdata<="010011001";
when"0110"=>rdata<="010000001";
when"0100"=>rdata<="000010101";
when"0101"=>rdata<="001010101";
when"0111"=>rdata<="001010111";
when"1000"=>rdata<="001010110";
whenothers=>rdata<="000000000";
endcase;
endprocess;
oen<=rdata(0);
we1<=rdata
(1);
we2<=rdata
(2);
gwe1<=rdata(3);
oen_n1<=rdata(4);
gwe2<=rdata(5);
oen_n2<=rdata(6);
gwe3<=rdata(7);
oen_n3<=rdata(8);
endBehavioral;
data_bus改编代码
----------------------------------------------------------------------------------
--Company:
--Engineer:
--
--CreateDate:
16:
56:
3203/08/2013
--DesignName:
--ModuleName:
data_bus-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Description:
--
--Dependencies:
--
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
--
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitydata_busis
Port(clk:
inSTD_LOGIC;
data_in1:
inSTD_LOGIC_VECTOR(3downto0);
data_in2:
inSTD_LOGIC_VECTOR(3downto0);
data_in3:
inSTD_LOGIC_VECTOR(3downto0);
data_in4:
inSTD_LOGIC_VECTOR(3downto0);
data_out1:
outSTD_LOGIC_VECTOR(3downto0);
data_out2:
outSTD_LOGIC_VECTOR(3downto0);
data_out3:
outSTD_LOGIC_VECTOR(3downto0);
data_out4:
outSTD_LOGIC_VECTOR(3downto0);
data_io1:
inoutSTD_LOGIC_VECTOR(3downto0);
data_io2:
inoutSTD_LOGIC_VECTOR(3downto0);
we1:
inSTD_LOGIC;
we2:
inSTD_LOGIC;
we3:
inSTD_LOGIC;
we4:
inSTD_LOGIC;
we_io1:
inSTD_LOGIC;
we_io2:
inSTD_LOGIC);
enddata_bus;
architectureBehavioralofdata_busis
signalbus_data_reg:
STD_LOGIC_VECTOR(3downto0);
signalout_en:
STD_LOGIC;
begin
out_en<='0'when(we1='1'orwe2='1'orwe3='1'orwe4='1'orwe_io1='1'orwe_io2='1')else'1';
data_io1<=bus_data_regwhenout_en='1'else"ZZZZ";
data_io2<=bus_data_regwhenout_en='1'else"ZZZZ";
data_out1<=bus_data_reg;
data_out2<=bus_data_reg;
data_out3<=bus_data_reg;
data_out4<=bus_data_reg;
process(clk)
begin
ifclk'eventandclk='1'then
ifwe1='1'then
bus_data_reg<=data_in1;
elsifwe2='1'then
bus_data_reg<=data_in2;
elsifwe3='1'then
bus_data_reg<=data_in3;
elsifwe4='1'then
bus_data_reg<=data_in4;
elsifwe_io1='1'then
bus_data_reg<=data_io1;
elsifwe_io2='1'then
bus_data_reg<=data_io2;
endif;
endif;
endprocess;
endBehavioral;
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