出租车.docx
- 文档编号:6956990
- 上传时间:2023-05-10
- 格式:DOCX
- 页数:26
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出租车.docx
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出租车
出
租
车
计
费
器
实
习
报
告
班级:
08电气自动化
组长:
黄玲
副组长:
张伟伟
组员:
朱玉英李鹏
王士斗黄金龙
实验原理:
费用的计算是按里程收费,出租车的起价为5元,当里程小于3km时,去年起价计算;当里程大于3km时,按每千米1.3元计算。
等待时间累计超过2min按每分钟1.5元计算。
并能显示行驶里程数,等待时间,总费用。
设计的主要技术指标如下:
计价范围:
0~~999.9元;计价分辨率:
0.1元。
计程范围:
0~99km;计程分辨率;1千米。
计时范围:
0~59min;计时分辨率,分。
顶层文件设计:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitytaxi_cis
port(clk:
instd_logic;--时钟信号
start:
instd_logic;--计费开始信号
stop:
instd_logic;--等待信号
fin:
instd_logic;--里程脉冲信号
sg:
outstd_logic_vector(6downto0);--duanma
bt:
outstd_logic_vector(7downto0));--weima
endtaxi_c;
architecturebehavioraloftaxi_cis
signalf_1:
std_logic;--频率为1Hz的信号
signalq_1:
integerrange0to99;--分频系数
signalw:
integerrange0to59;--计时按分钟算
signalc3,c2,c1,c0:
std_logic_vector(3downto0);--制费用计数器
signalk1,k0:
std_logic_vector(3downto0):
="0000";--公里计数器
signalm1:
std_logic_vector(2downto0):
="000";--分的十位计数器
signalm0:
std_logic_vector(3downto0):
="0000";--分的个位计数器
signalen1,en0:
std_logic;--使能信号
signaltemp0,temp1:
std_logic_vector(3downto0);
signalcounter:
std_logic_vector(31downto0);
componentdiv
port(clk,start:
instd_logic;
q_1:
bufferintegerrange0to99;
f_1:
bufferstd_logic);
endcomponent;
componentjifei
port(start,clk,en0,en1:
instd_logic;
k0:
instd_logic_vector(3downto0):
="0000";
m0:
instd_logic_vector(3downto0):
="0000";
c3,c2,c1,c0:
bufferstd_logic_vector;
temp0:
bufferstd_logic_vector(3downto0);
temp1:
bufferstd_logic_vector(3downto0));
endcomponent;
componentjishi
port(f_1,start,stop:
instd_logic;
m0,m1:
bufferstd_logic_vector);
endcomponent;
componentkongzhi
port(clk,start,stop:
instd_logic;
k0,k1:
instd_logic_vector(3downto0):
="0000";
m0:
instd_logic_vector(3downto0):
="0000";
m1:
instd_logic_vector(2downto0):
="000";
en0,en1:
outstd_logic);
endcomponent;
componentlichji
port(start,fin,stop:
instd_logic;
k0,k1:
bufferstd_logic_vector(3downto0):
="0000");
endcomponent;
componentxianshi
port(f_1,start:
instd_logic;
k0,k1:
instd_logic_vector(3downto0):
="0000";
m0:
instd_logic_vector(3downto0):
="0000";
m1:
instd_logic_vector(2downto0):
="000";
c3,c2,c1,c0:
instd_logic_vector;
km1,km0,min1,min0:
outstd_logic_vector;
cha3,cha2,cha1,cha0:
outstd_logic_vector);
endcomponent;
componentscan_led
PORT(CLK:
INSTD_LOGIC;
count:
inSTD_LOGIC_VECTOR(31DOWNTO0);
sg:
OUTSTD_LOGIC_VECTOR(6DOWNTO0);--段控制信号输出
bt:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));--位控制信号输出
endcomponent;
begin
u1:
divportmap(clk=>clk,start=>start,q_1=>q_1,f_1=>f_1);
u2:
jifeiportmap(en0=>en0,en1=>en1,start=>start,clk=>clk,k0=>temp0,m0=>temp1,c3=>c3,c2=>c2,c1=>c1,c0=>c0);
u3:
jishiportmap(stop=>stop,start=>start,f_1=>f_1,m0=>m0,m1=>m1);
u4:
kongzhiportmap(start=>start,stop=>stop,clk=>clk,k0=>k0,k1=>k1,m0=>m0,m1=>m1,en0=>en0,en1=>en1);
u5:
lichjiportmap(fin=>fin,start=>start,stop=>stop,k0=>k0,k1=>k1);
u6:
xianshiportmap(f_1=>f_1,start=>start,m0=>m0,m1=>m1,k0=>k0,k1=>k1,c3=>c3,c2=>c2,c1=>c1,c0=>c0,km1=>counter(31downto28),km0=>counter(27downto24),min1=>counter(23downto20),min0=>counter(19downto16),cha3=>counter(15downto12),cha2=>counter(11downto8),cha1=>counter(7downto4),cha0=>counter
(3downto0));
u7:
scan_ledportmap(clk=>clk,count=>counter,sg=>sg,bt=>bt);
endarchitecturebehavioral;
顶层波形图
顶层RTL
分频文件程序:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitydivis
port(clk,start:
instd_logic;
q_1:
bufferintegerrange0to99;
f_1:
bufferstd_logic);
endentitydiv;
architectureoneofdivis
begin
process(clk,start)
begin
ifclk'eventandclk='1'then
ifstart='0'thenf_1<='0';q_1<=0;
else
ifq_1=99thenq_1<=0;f_1<='1';--此IF语句得到频率为1Hz的信号
elseq_1<=q_1+1;f_1<='0';
endif;
endif;
endif;
endprocess;
endarchitectureone;
分频RTL图
分频波形图
里程程序设计:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitylichjiis
port(start,fin,stop:
instd_logic;
k0,k1:
bufferstd_logic_vector(3downto0):
="0000");
endentity;
architectureoneoflichjiis
begin
process(fin)
begin
iffin'eventandfin='1'then
ifstart='0'then
k1<="0000";k0<="0000";
elsifstop='0'then--IF语句完成等待计时
ifk0="1001"then
k0<="0000";
ifk1="1001"then
k1<="0000";
elsek1<=k1+1;
endif;
else
k0<=k0+1;
endif;
endif;
endif;
endprocess;
endarchitecture;
里程RTL图
里程波形图
计时程序设计:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityjishiis
port(f_1,start,stop:
instd_logic;
--w:
bufferintegerrange0to59;
m1:
bufferstd_logic_vector(2downto0);
m0:
bufferstd_logic_vector(3downto0));
endentity;
architectureacofjishiis
begin
process(f_1)
begin
iff_1'eventandf_1='1'then
ifstart='0'then--w<=0;
m1<="000";
m0<="0000";
elsifstop='1'then
--ifw=59then
--w<=0;
ifm0="1001"then
m0<="0000";--此IF语句完成分计数
ifm1="101"then
m1<="000";
elsem1<=m1+1;
endif;
elsem0<=m0+1;
endif;
--elsew<=w+1;
endif;
endif;
endprocess;
endarchitecture;
计时RTL
计时波形图
计费程序设计:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityjifeiis
port(start,clk,en0,en1:
instd_logic;
k0,m0:
instd_logic_vector(3downto0):
="0000";
c3,c2,c1,c0:
bufferstd_logic_vector(3downto0);
temp0:
bufferstd_logic_vector(3downto0);
temp1:
bufferstd_logic_vector(3downto0));
endentity;
architectureshuofjifeiis
begin
process(clk,start)
variablec13,c15:
integer;
begin
ifstart='0'then
c3<="0000";c2<="0000";c1<="0101";c0<="0000";
c13:
=0;c15:
=0;temp0<="0000";temp1<="0000";
elsifclk'eventandclk='1'then
if(en0='1')then
if(c13<13)then
c13:
=c13+1;
if(c13=1)then
temp0<=k0;
endif;
ifc0="1001"thenc0<="0000";--此IF语句完成对费用的计数
ifc1="1001"thenc1<="0000";
ifc2="1001"thenc2<="0000";
ifc3="1001"thenc3<="0000";
elsec3<=c3+1;
endif;
elsec2<=c2+1;
endif;
elsec1<=c1+1;
endif;
elsec0<=c0+1;
endif;
elsif(k0/=temp0)thenc13:
=0;
endif;
elsif(en1='1')then
if(c15<15)then
c15:
=c15+1;
if(c15=1)then
temp1<=m0;
endif;
ifc0="1001"thenc0<="0000";--此IF语句完成对费用的计数
ifc1="1001"thenc1<="0000";
ifc2="1001"thenc2<="0000";
ifc3="1001"thenc3<="0000";
elsec3<=c3+1;
endif;
elsec2<=c2+1;
endif;
elsec1<=c1+1;
endif;
elsec0<=c0+1;
endif;
elsif(m0/=temp1)thenc15:
=0;
endif;
endif;
endif;
endprocess;
endarchitecture;
计费RTL
计费波形图
控制程序设计:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitykongzhiis
port(clk,start,stop:
instd_logic;
k0,k1:
instd_logic_vector(3downto0);
m0:
instd_logic_vector(3downto0);
m1:
instd_logic_vector(2downto0);
en0,en1:
outstd_logic);
endentity;
architectureoneofkongzhiis
begin
process(clk)
begin
ifclk'eventandclk='1'then
ifstart='0'then
en0<='0';
en1<='0';
elsifstop='0'then
en1<='0';
ifk1&k0>"00000011"then
en0<='1';
else
en0<='0';
endif;
elsifstop='1'then
en0<='0';
ifm1&m0>"0000010"then
en1<='1';
elseen1<='0';
endif;
endif;
endif;
endprocess;
endarchitecture;
控制波形图
控制RTL
显示程序设计:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYSCAN_LEDIS
PORT(CLK:
INSTD_LOGIC;
count:
inSTD_LOGIC_VECTOR(31DOWNTO0);
SG:
OUTSTD_LOGIC_VECTOR(6DOWNTO0);--段控制信号输出
BT:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));--位控制信号输出
END;
ARCHITECTUREoneOFSCAN_LEDIS
SIGNALCNT8:
STD_LOGIC_VECTOR(2DOWNTO0);
SIGNALA:
INTEGERRANGE0TO15;
BEGIN
P1:
process(CNT8)
BEGIN
CASECNT8IS
WHEN"000"=>BT<="00000001";A<=conv_integer(count(27downto24));--公里个位
WHEN"001"=>BT<="00000010";A<=conv_integer(count(31downto28));--公里十位
WHEN"010"=>BT<="00000100";A<=conv_integer(count(19downto16));--分个位
WHEN"011"=>BT<="00001000";A<=conv_integer(count(23downto20));--分十位
WHEN"100"=>BT<="00010000";A<=conv_integer(count(3downto0));--角
WHEN"101"=>BT<="00100000";A<=conv_integer(count(7downto4));--元
WHEN"110"=>BT<="01000000";A<=conv_integer(count(11downto8));--十位
WHEN"111"=>BT<="10000000";A<=conv_integer(count(15downto12));--百位
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESSp1;
p2:
PROCESS(clk)
BEGIN
IFclk'eventANDCLK='1'THENCNT8<=CNT8+1;
ENDIF;
ENDPROCESSP2;
P3:
process(A)--译码电路
BEGIN
CASEAIS
WHEN0=>SG<="0111111";WHEN1=>SG<="0000110";
WHEN2=>SG<="1011011";WHEN3=>SG<="1001111";
WHEN4=>SG<="1100110";WHEN5=>SG<="1101101";
WHEN6=>SG<="1111101";WHEN7=>SG<="0000111";
WHEN8=>SG<="1111111";WHEN9=>SG<="1101111";
WHEN10=>SG<="1000000";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESSP3;
END;
Scan_led的波形图
引脚锁定:
感受:
实训心得
2010.5.24
1:
将大程序拆分为子模块,设计调用模块的顶层文件
2010.5.25
1:
开始对各个模块进行综合,有的模块发现错误,点击错误报告,锁定错误范围后,进行了一一排除。
2:
各个模块综合成功后,开始对各个模块进行仿真测试,看是否满足要求。
2010.5.26
1:
进行顶层文件综合与仿真测试。
1:
查看程序发现停止时计算停留时间模块不能正确工作,调出计时子模块后,开始修改,编译,仿真,发现有一个if语句的判断符号写成了赋值符号,致使此if语句不能正确运行!
2:
引脚锁定时发现只有四个数码管的引脚,但程序需要用八个,后只接了四个,分别用于显示出租车停留时间和出租车行驶里程,使其余显示总费用的四个悬空,进行下载验证,发现程序设计正确
2010.5.27
1:
掌握了怎样用mux_plusⅡ烧入程序,将程序的引脚锁定后烧入芯片,进行硬件测试,达到预期结果,试验成功,经老师验证合格!
2010.5.28
1:
老师要求需用八个数码管,并给出一个译码模块,所以,我们立刻将原程序备份后开始修改程序,将数码管由静态显示变为动态显示!
2:
经过一个小时的修改,程序编译成功,继而引脚锁定,程序下载,进行硬件测试,实验结果正确,设计成功!
二:
实验感受
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- 关 键 词:
- 出租车