光伏发电逆变器毕业论文中英文资料外文翻译文献.docx
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光伏发电逆变器毕业论文中英文资料外文翻译文献.docx
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毕业论文
光伏发电逆变器毕业论文中英文资料外文翻译文献
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TMS320LF2407,TMS320LF2406,TMS320LF2402TMS320LC2406,TMS320LC2404,MS320LC2402DSPCONTROLLERS
TheTMS320LF240xandTMS320LC240xdevices,newmembersofthe‘24xfamilyofdigitalsignalprocessor(DSP)controllers,arepartoftheC2000platformoffixed-pointDSPs.
The‘240xdevicesoffertheenhancedTMS320architecturaldesignofthe‘C2xxcoreCPUforlow-cost,low-power,high-performanceprocessingcapabilities.Severaladvancedperipherals,optimizedfordigitalmotorandmotioncontrolapplications,havebeenintegratedtoprovideatruesinglechipDSPcontroller.Whilecode-compatiblewiththeexisting‘24xDSPcontrollerdevices,the‘240xoffersincreasedprocessingperformance(30MIPS)andahigherlevelofperipheralintegration.SeetheTMS320x240xdevicesummarysectionfordevice-specificfeatures.
The‘240xfamilyoffersanarrayofmemorysizesanddifferentperipheralstailoredtomeet
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thespecificprice/performancepointsrequiredbyvariousapplications.Flash-baseddevicesofupto32Kwordsofferareprogrammablesolutionusefulfor:
uApplicationsrequiringfieldprogrammabilityupgrades.
uDevelopmentandinitialprototypingofapplicationsthatmigratetoROM-baseddevices.
FlashdevicesandcorrespondingROMdevicesarefullypin-to-pincompatible.Notethatflash-baseddevicescontaina256-wordbootROMtofacilitatein-circuitprogramming.
All‘240xdevicesofferatleastoneeventmanagermodulewhichhasbeenoptimizedfordigitalmotorcontrolandpowerconversionapplications.Capabilitiesofthismoduleincludecentered- and/oredge-aligned PWM generation, programmable deadband to preventshoot-throughfaults,andsynchronizedanalog-to-digitalconversion.Deviceswithdualeventmanagersenablemultiplemotorand/orconvertercontrolwithasingle ‗240xDSPcontroller.
Thehighperformance,10-bitanalog-to-digitalconverter(ADC)hasaminimumconversiontimeof500nsandoffersupto16channelsofanaloginput.TheautosequencingcapabilityoftheADCallowsamaximumof16conversionstotakeplaceinasingleconversionsessionwithoutanyCPUoverhead.
Aserialcommunicationsinterface(SCI)isintegratedonalldevicestoprovideasynchronouscommunicationtootherdevicesinthesystem.Forsystemsrequiringadditionalcommunicationinterfaces;the‘2407,‘2406,and‘2404offera16-bitsynchronousserialperipheralinterface(SPI).The‘2407and‘2406offeracontrollerareanetwork(CAN)communicationsmodulethatmeets2.0Bspecifications.Tomaximizedeviceflexibility,functionalpinsarealsoconfigurableasgeneralpurposeinputs/outputs(GPIO).
Tostreamlinedevelopmenttime,JTAG-compliantscan-basedemulationhasbeenintegratedintoalldevices.Thisprovidesnon-intrusivereal-timecapabilitiesrequiredtodebugdigitalcontrolsystems.AcompletesuiteofcodegenerationtoolsfromCcompilerstotheindustry-standardCodeComposerdebuggersupportsthisfamily.Numerousthirdpartydevelopersnotonlyofferdevice-leveldevelopmenttools,butalsosystem-leveldesignanddevelopmentsupport.
PERIPHERALS
TheintegratedperipheralsoftheTMS320x240xaredescribedinthefollowingsubsections:
lTwoevent-managermodules(EVA,EVB)
lEnhancedanalog-to-digitalconverter(ADC)module
lControllerareanetwork(CAN)module
lSerialcommunicationsinterface(SCI)module
lSerialperipheralinterface(SPI)module
lPLL-basedclockmodule
lDigitalI/Oandsharedpinfunctions
lExternalmemoryinterfaces(‘LF2407only)
lWatchdog(WD)timermodule
Eventmanagermodules(EVA,EVB)
Theevent-managermodulesincludegeneral-purpose(GP)timers,full-compare/PWMunits,captureunits,andquadrature-encoderpulse(QEP)circuits.EVA‘sandEVB‘stimers,compareunits,andcaptureunitsfunctionidentically.However,timer/unitnamesdifferforEVAandEVB.Table1showsthemoduleandsignalnamesused.Table1showsthefeaturesandfunctionalityavailablefortheevent-managermodulesandhighlightsEVAnomenclature.
EventmanagersAandBhaveidenticalperipheralregistersetswithEVAstartingat7400handEVBstartingat7500h.TheparagraphsinthissectiondescribethefunctionofGPtimers,compareunits,captureunits,andQEPsusingEVAnomenclature.TheseparagraphsareapplicabletoEVBwithregardtofunction—however,module/signalnameswoulddiffer.
EVENTMANAGER
MODULES
EVA
EVB
SIGNAL
SIGNAL
GPTimers
CompareUnits
Table1.ModuleandSignalNamesforEVAandEVB
MODULE
MODULE
Timer1
T1PWM/T1CMP
Timer3
T3PWM/T3CMP
Timer2
T2PWM/T2CMP
Timer4
T4PWM/T4CMP
Compare1
PWM1/2
Compare4
PWM7/8
Compare2
PWM3/4
Compare5
PWM9/10
Compare3
PWM5/6
Compare6
PWM11/12
CaptureUnits
QEP
ExternalInputs
DirectionExternal
Clock
TDIRA
TCLKINA
Direction
ExternalClock
TDIRB
TCLKINB
Capture1
CAP1
Capture4
CAP4
Capture2
CAP2
Capture5
CAP5
Capture3
CAP3
Capture6
CAP6
QEP1
QEP1
QEP3
QEP3
QEP2
QEP2
QEP4
QEP4
General-purpose(GP)timers
TherearetwoGPtimers:
TheGPtimerx(x=1or2forEVA;x=3or4forEVB)includes:
lA16-bittimer,up-/down-counter,TxCNT,forreadsorwrites
lA16-bittimer-compareregister,TxCMPR(double-bufferedwithshadowregister),forreadsorwrites
lA16-bittimer-period register,TxPR(double-bufferedwithshadowregister),forreadsorwrites
lA16-bittimer-controlregister,TxCON,forreadsorwrites
lSelectableinternalorexternalinputclocks
lAprogrammableprescalerforinternalorexternalclockinputs
lControlandinterruptlogic,forfourmaskableinterrupts:
underflow,overflow,timercompare,andperiodinterrupts
lAselectabledirectioninputpin(TDIR)(tocountupordownwhendirectionalup-/down-countmodeisselected)
TheGPtimerscanbeoperatedindependentlyorsynchronizedwitheachother.ThecompareregisterassociatedwitheachGPtimercanbeusedforcomparefunctionandPWM-waveformgeneration.TherearethreecontinuousmodesofoperationsforeachGPtimerinup-orup/down-countingoperations.InternalorexternalinputclockswithprogrammableprescalerareusedforeachGPtimer.GPtimersalsoprovidethetimebasefortheotherevent-managersubmodules:
GPtimer1forallthecomparesandPWMcircuits,GPtimer2/1forthecaptureunitsandthequadrature-pulsecountingoperations.Double-bufferingoftheperiodandcompareregistersallowsprogrammablechangeofthetimer(PWM)periodandthecompare/PWMpulsewidthasneeded.
Full-compareunits
Therearethreefull-compareunitsoneacheventmanager.ThesecompareunitsuseGPtimer1asthetimebaseandgeneratesixoutputsforcompareandPWM-waveformgenerationusingprogrammabledeadbandcircuit.Thestateofeachofthesixoutputsisconfiguredindependently.Thecompareregistersofthecompareunitsaredouble-buffered,allowingprogrammablechangeofthecompare/PWMpulsewidthsasneeded.
Programmabledeadbandgenerator
Thedeadbandgeneratorcircuitincludesthree8-bitcountersandan8-bitcompareregister.Desireddeadbandvalues(from0to24µs)canbeprogrammedintothecompareregisterfortheoutputsofthethreecompareunits.Thedeadbandgenerationcanbeenabled/disabledforeachcompareunitoutputindividually.Thedeadband-generatorcircuitproducestwooutputs(withor
withoutdeadbandzone)foreachcompareunitoutputsignal.Theoutputstatesofthedeadbandgeneratorareconfigurableandchangeableasneededbywayofthedouble-bufferedACTRregister.
PWMwaveformgeneration
UptoeightPWMwaveforms(outputs)canbegeneratedsimultaneouslybyeacheventmanager:
threeindependentpairs(sixoutputs)bythethreefull-compareunitswithprogrammabledeadbands,andtwoindependentPWMsbytheGP-timercompares.
PWMcharacteristics
CharacteristicsofthePWMsareasfollows:
l16-bitregisters
lProgrammabledeadbandforthePWMoutputpairs,from0to24µs
lMinimumdeadbandwidthof50ns
lChangeofthePWMcarrierfrequencyforPWMfrequencywobblingasneeded
lChangeofthePWMpulsewidthswithinandaftereachPWMperiodasneeded
lExternal-maskablepoweranddrive-protectioninterrupts
lPulse-pattern-generator circuit, for programmable generation of asymmetric,symmetric,andfour-spacevectorPWMwaveforms
lMinimizedCPUoverheadusingauto-reloadofthecompareandperiodregisters
Captureunit
Thecaptureunitprovidesaloggingfunctionfordifferenteventsortransitions.ThevaluesoftheGPtimer2counterarecapturedandstoredinthetwo-level-deepFIFOstackswhenselectedtransitionsaredetectedoncaptureinputpins,CAPx(x=1,2,or3forEVA;andx=4,5,or6forEVB).Thecaptureunitconsistsofthreecapturecircuits.
Captureunitsincludethefollowingfeatures:
lOne16-bitcapturecontrolregister,CAPCON(R/W)
lOne16-bitcaptureFIFOstatusregister,CAPFIFO(eightMSBsareread-only,eightLSBsarewrite-only)
lSelectionofGPtimer2asthetimebase
lThree16-bit2-level-deepFIFOstacks,oneforeachcaptureunit
lThreeSchmitt-triggeredcaptureinputpins(CAP1,CAP2,andCAP3)—oneinputpinpercaptureunit.[Allinputsaresynchronizedwiththedevice(CPU)clock.Inorderforatransitiontobecaptured,theinputmustholdatitscurrentleveltomeettworisingedgesofthedeviceclock.TheinputpinsCAP1andCAP2canalsobeusedasQEP
inputstotheQEPcircuit.]
lUser-specifiedtransition(risingedge,fallingedge,orbothedges)detection
lThreemaskableinterruptflags,oneforeachcaptureunit
Enhancedanalog-to-digitalconverter(ADC)module
AsimplifiedfunctionalblockdiagramoftheADCmoduleisshowninFigure1.TheADCmoduleconsistsofa10-bit
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