VHDL数字电路课程实验报告.docx
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VHDL数字电路课程实验报告.docx
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VHDL数字电路课程实验报告
VHDL数字电路课程实验报告
实验一8分频器
一、实验要求:
分别用信号量和变量实现八分频器
二、实验过程:
1、代码:
8分频器vhd
libraryieee;
useieee.std_logic_1164.all;
entityfreq_divideris
port(clk:
instd_logic;
out1,out2:
bufferbit);
endfreq_divider;
architectureexampleoffreq_divideris
signalcount1:
integerrange0to7;
begin
process(clk)
variablecount2:
integerrange0to7;
begin
if(clk'eventandclk='1')then
count1<=count1+1;
count2:
=count2+1;
if(count1=3)then
out1<=notout1;
count1<=0;
endif;
if(count2=4)then
out2<=notout2;
count2:
=0;
endif;
endif;
endprocess;
endexample;
八分频器tb
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYfd_tbis
ENDfd_tb;
architecturebehavioroffd_tbis
componentfreq_divider
port(clk:
INSTD_LOGIC;
out1,out2:
bufferbit);
endcomponent;
signalclk:
std_logic;
signalout1,out2:
bit;
begin
u1:
freq_dividerportmap(clk,out1,out2);
process
begin
clk<='0';
waitfor50ns;
loop
clk<=notclk;
waitfor25ns;
endloop;
endprocess;
endbehavior;
2、结果图:
实验二实现例8.6
一、实验要求:
电路只有一个输入时钟信号,输出信号在适中的两个边沿都会发生变化
二、实验内容:
1、代码
信号发生器vhd
ENTITYsignal_genIS
PORT(clk:
INBIT;
outp:
OUTBIT);
ENDsignal_gen;
ARCHITECTUREfsmOFsignal_genIS
TYPEstateIS(one,two,three);
SIGNALpr_state1,nx_state1:
state;
SIGNALpr_state2,nx_state2:
state;
SIGNALout1,out2:
BIT;
BEGIN
PROCESS(clk)
BEGIN
IF(clk'EVENTANDclk='1')THEN
pr_state1<=nx_state1;
ENDIF;
ENDPROCESS;
PROCESS(clk)
BEGIN
IF(clk'EVENTANDclk='0')THEN
pr_state2<=nx_state2;
ENDIF;
ENDPROCESS;
PROCESS(pr_state1)
BEGIN
CASEpr_state1IS
WHENone=>
out1<='0';
nx_state1<=two;
WHENtwo=>
out1<='1';
nx_state1<=three;
WHENthree=>
out1<='1';
nx_state1<=one;
ENDCASE;
ENDPROCESS;
PROCESS(pr_state2)
BEGIN
CASEpr_state2IS
WHENone=>
out2<='1';
nx_state2<=two;
WHENtwo=>
out2<='0';
nx_state2<=three;
WHENthree=>
out2<='1';
nx_state2<=one;
ENDCASE;
ENDPROCESS;
outp<=out1ANDout2;
ENDfsm;
信号发生器tb
entitytb_fsmis
endtb_fsm;
architecturebehavioroftb_fsmis
componentsignal_genis
port(clk:
inbit;
outp:
outbit);
endcomponent;
signalclk,outp:
bit;
begin
u1:
signal_genportmap(clk,outp);
process
begin
clk<='0';
waitfor20ns;
loop
clk<=notclk;
waitfor10ns;
endloop;
endprocess;
endbehavior;
2、结果图
实验三常数比较器
一、实验要求常数比较器,用于比较的变量位宽应大于等于常数
二、实验内容
1、代码
常数比较器vhd
LIBRARYieee;
USEieee.std_logic_1164.all;
entitycompareis
port(b:
inintegerrange0to15;
x1,x2,x3:
outstd_logic);
endcompare;
architecturecompareofcompareis
constanta:
integer:
=10;
begin
x1<='1'whena>belse'0';
x2<='1'whena=belse'0';
x3<='1'whena endcompare; 常数比较器tb LIBRARYieee; USEieee.std_logic_1164.all; entitytb_compareis endtb_compare; architecturebehavioroftb_compareis componentcompare port(b: inintegerrange0to15; x1,x2,x3: outstd_logic); endcomponent; signalb: integer; signalx1,x2,x3: std_logic; begin u1: compareportmap(b,x1,x2,x3); process begin b<=5;waitfor10ns; b<=8;waitfor10ns; b<=10;waitfor10ns; b<=13;waitfor10ns; b<=10;waitfor10ns; b<=3;waitfor10ns; endprocess; endbehavior; 2、结果图 实验四序列检测器 一、实验要求序列检测’1001’弱检测到,输出‘1‘,否则输出’0‘ 二、实验内容 1、状态图 2、代码 序列检测器vhd libraryieee; useieee.std_logic_1164.all; entitystring_detectoris port(datain,clk: inbit; q: outbit); endstring_detector; architecturesdofstring_detectoris typestateis(zero,one,two,three,four); signalpr_state,nx_state: state; begin process(clk) begin if(clk'eventandclk='1')then pr_state<=nx_state; endif; endprocess; process(datain,pr_state) begin casepr_stateis whenzero=> q<='0'; if(datain='1')thennx_state<=one; elsenx_state<=zero; endif; whenone=> q<='0'; if(datain='0')thennx_state<=two; elsenx_state<=zero; endif; whentwo=> q<='0'; if(datain='0')thennx_state<=three; elsenx_state<=zero; endif; whenthree=> q<='0'; if(datain='1')thennx_state<=four; elsenx_state<=zero; endif; whenfour=> q<='1'; nx_state<=zero; endcase; endprocess; endsd; 序列检测器tb ------------------------------------------------------------------ libraryieee; useieee.std_logic_1164.all; ------------------------------------------------------------------ entitytestBenchis endtestBench; ------------------------------------------------------------------ architecturetestoftestBenchis componentstring_detectoris port(datain,clk: inbit; q: outbit); endcomponent; signaldatain,clk: bit; signalq: bit; begin SD: string_detectorportmap(datain,clk,q); process begin foriin0to100loop clk<='0'; waitfor10ns; clk<='1'; waitfor10ns; endloop; endprocess; process begin din<='1'; waitfor20ns; din<='0'; waitfor20ns; din<='0'; waitfor20ns; din<='0'; waitfor20ns; din<='1'; waitfor20ns; din<='0'; waitfor20ns; din<='0'; waitfor20ns; din<='1'; waitfor20ns; din<='0'; waitfor20ns; din<='1'; waitfor20ns; din<='0'; waitfor20ns; endprocess; endtest; 3、结果图
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