EDA技术与VHDL课后答案第3版潘松 黄继业Word文档格式.docx
- 文档编号:350569
- 上传时间:2023-04-28
- 格式:DOCX
- 页数:21
- 大小:18.16KB
EDA技术与VHDL课后答案第3版潘松 黄继业Word文档格式.docx
《EDA技术与VHDL课后答案第3版潘松 黄继业Word文档格式.docx》由会员分享,可在线阅读,更多相关《EDA技术与VHDL课后答案第3版潘松 黄继业Word文档格式.docx(21页珍藏版)》请在冰点文库上搜索。
y<
WHEN“01”=>
WHEN“10”=>
WHEN“11”=>
WHENOTHERS=>
NULL;
ENDCASE;
ENDARCHITECTUREtwo;
3-3程序:
ENTITYMUXKIS
PORT(s0,s1:
a1,a2,a3:
outy:
ENDENTITYMUXK;
ARCHITECTUREdoubleOFMUXKIS
SIGNALtmp:
STD_LOGIC;
--内部连接线
p_MUX21A_u1:
PROCESS(u1_s,u1_a,u1_b,u1_y)
SIGNALu1_s,u1_a,u1_b,u1_y:
IFu1_s=’0’THENu1_y<
=u1_a;
ELSIFu1_y<
=u1_b;
ELSEu1_y<
=NULL;
ENDPROCESSp_MUX21A_u1;
p_MUX21A_u2:
PROCESS(u2_s,u2_a,u2_b,u2_y)
SIGNALu2_s,u2_a,u2_b,u2_y:
BEGIN
IFu2_s=’0’THENu2_y<
=u2_a;
ELSIFu2_y<
=u2_b;
ELSEu2_y<
ENDPROCESSp_MUX21A_u2;
u1_s<
=s0;
u1_a<
=a2;
u1_b<
=a3;
tmp<
=u1_y;
u2_s<
=s1;
u2_a<
=a1;
u2_b<
=tmp;
outy<
=u2_y;
ENDARCHITECTUREdouble;
3-4程序:
(1)1位半减器
1位半减器的设计选用
(2)图,两种表达方式:
一、LIBRARYIEEE;
ENTITYh_suberIS
PORT(x,y:
s_out,diff:
ENDENTITYh_suber;
ARCHITECTUREfhd1OFh_suberIS
diff<
=xXORy;
s_out<
=(NOTa)ANDb;
ENDARCHITECTUREfhd1;
二、LIBRARYIEEE;
=x&
y;
s_out<
=’0’;
=’1’;
ENDARCHITECTUREfhd1;
或门逻辑描述:
ENTITYorIS
PORT(a,b:
c:
ENDENTITYor;
ARCHITECTUREoneOForIS
c<
=aORb;
ENDARCHITECTUREone;
1位全减器:
ENTITYf_suberIS
PORT(x,y,sub_in:
sub_out,diffr:
ENDENTITYf_suber;
ARCHITECTUREfhd1OFf_suberIS
COMPONENTh_suberIS
ENDCOMPONENTh_suber;
COMPONENTorIS
ENDCOMPONENTor;
SIGNALd,e,f:
u1:
h_suberPORTMAP(x=>
x,y=>
y,diff=>
d,s_out=>
e);
u2:
d,y=>
sub_in,diff=>
diffr,s_out=>
f);
u3:
orPORTMAP(a=>
f,b=>
e,c=>
sub_out);
(2)8位减法器:
f_suber
sub_inxy
sub_out
diffr
x
y
1
2
3
4
5
6
7
abc
d
efg
u0u1u2u3
u4u5u6u7
ENTITY8f_suberIS
PORT(x0,x1,x2,x3,x4,x5,x6,x7:
y0,y1,y2,y3,y4,y5,y6,y7:
sub_in:
sub_out:
OUTSTD_LOGIC;
diffr0,diffr1,diffr2,diffr3:
diffr4,diffr5,diffr6,diffr7:
ENDENTITY8f_suber;
ARCHITECTURE8fhd1OF8f_suberIS
COMPONENTf_suberIS
ENDCOMPONENTf_suber;
SIGNALa,b,c,d,e,f,g:
u0:
f_suberPORTMAP(x=>
x0,y=>
y0,sub_in=>
sub_out=>
a,
diff=>
diff0);
x1,y=>
y1,sub_in=>
a,sub_out=>
b,
diff1);
f_suberPORTMAP(x=>
x2,y=>
y2,sub_in=>
b,sub_out=>
c,
diff2);
u3:
x3,y=>
y3,sub_in=>
c,sub_out=>
d,
diff3);
u4:
x4,y=>
y4,sub_in=>
d,sub_out=>
e,
diff4);
u5:
x5,y=>
y5,sub_in=>
e,sub_out=>
f,
diff5);
u6:
x6,y=>
y6,sub_in=>
f,sub_out=>
g,
diff6);
u7:
x7,y=>
y7,sub_in=>
g,sub_out=>
sub_out,diff=>
diff7);
ENDARCHITECTURE8fhd1;
3-5程序:
或非门逻辑描述:
ENTITYnorIS
PORT(d,e:
f:
ENDENTITYnor;
ARCHITECTUREoneOFnorIS
f<
=NOT(dORe);
时序电路描述:
ENTITYcircuitIS
PORT(CL,CLK0:
OUT1:
ENDENTITYcircuit;
ARCHITECTUREoneOFcircuitIS
COMPONENTDFF1IS
PORT(CLK:
D:
Q:
ENDCOMPONENTDFF1;
COMPONENTnorIS
ENDCOMPONENTnor;
COMPONENTnotIS
PORT(g:
h:
ENDCOMPONENTnot;
SIGNALa,b,c:
u0:
norPORTMAP(d=>
c,e=>
CL,f=>
a);
u1:
DFF1PORTMAP(CLK=>
CLK0,D=>
a,Q=>
b);
u2:
notPORTMAP(g=>
b,g=>
c,h=>
OUT1);
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
程序1:
SIGNALA,EN:
PROCESS(A,EN)
VARIABLEB:
IFEN=‘1’THENB:
=A;
程序2:
ARCHITECTUREoneOFsampleIS
VARIABLEa,b,c:
=a+b;
程序3:
sel:
ENDENTITYmux21;
ARCHITECTUREoneOFmux21IS
IFsel=‘0’THENc<
ELSEc<
第4章QuartusII使用方法
4-1
第5章VHDL状态机
5-1例5-4(两个进程):
ENTITYMOORE1IS
PORT(DATAIN:
INSTD_LOGIC_VECTOR(1DOWNTO0);
CLK,RST:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDENTITYMOORE1;
ARCHITECTUREbehavOFMOORE1IS
TYPEST_TYPEIS(ST0,ST1,ST2,ST3,ST4);
SIGNALC_ST,N_ST:
ST_TYPE;
REG:
PROCESS(RST,CLK)
IFRST=’1’THENC_ST<
=ST0;
Q<
=”0000”;
ELSIFCLK’EVENTANDCLK=’1’THEN
C_ST<
=N_ST;
ENDIF;
ENDPROCESS;
COM:
PROCESS(C_ST,DATAIN)
CASEC_STIS
WHENST0=>
IFDATAIN=“10”THENN_ST<
=ST1;
ELSEN_ST<
=ST0;
Q<
=”1001”;
WHENST1=>
IFDATAIN=“11”THENN_ST<
=ST2;
=”0101”;
WHENST2=>
IFDATAIN=“01”THENN_ST<
=ST3;
=”1100”;
WHENST3=>
IFDATAIN=“00”THENN_ST<
=ST4;
=”0010”;
WHENST4=>
IFDATAIN=“11”THENN_ST<
=”1001”;
WHENOTHERS=>
N_ST<
ENDCASE;
ENDARCHITECTUREbehav;
5-2例5-5(单进程):
ENTITYMEALY1IS
PORT(CLK,DATAIN,RESET:
OUTSTD_LOGIC_VECTOR(4DOWNTO0));
ENDENTITYMEALY1;
ARCHITECTUREbehavOFMEALY1IS
TYPEstatesIS(st0,st1,st2,st3,st4);
SIGNALSTX:
states;
PROCESS(CLK,RESET)
IFRESET=‘1’THENSTX<
=st0;
ELSIFCLK’EVENTANDCLK=‘1’THEN
CASESTXIS
WHENst0=>
IFDATAIN=‘1’THENSTX<
=st1;
=”10000”;
ELSEQ<
=”01010”;
WHENst1=>
IFDATAIN=‘0’THENSTX<
=st2;
=”10111”;
=”10100”;
WHENst2=>
IFDATAIN=‘1’THENSTX<
=st3;
=”10101”;
=”10011”;
WHENst3=>
=st4;
=”11011”;
=”01001”;
WHENst4=>
=st0;
=”11101”;
=”01101”;
STX<
=st0;
=”00000”;
ENDCASE;
5-3序列检测器:
要求1:
要求2:
要求3:
5-4
5-5
第6章16位CISCCPU设计
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
第7章VHDL语句
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
第8章VHDL结构
8-1
8-2
8-3
8-4
8-5VHDL综合器支持的类型:
STRING、BIT;
8-6【例8-28】
--
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdecoder3t08IS
port(input:
INSTD_LOGIC_VECTOR(2DOWNTO0);
output:
OUTBIT_VECTOR(7DOWNTO0));
ENDENTITYdecoder3t08;
ARCHITECTUREbehaveOFdecoder3t08IS
output<
=“”SLLCONV_INTEGER(input);
inputoutput
000
001
010
011
100
101
110
111
ENDbehave;
8-7不能,因为求和操作符的操作数的数
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- EDA技术与VHDL课后答案第3版潘松 黄继业 EDA 技术 VHDL 课后 答案 版潘松 继业