秒表源程序.docx
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秒表源程序.docx
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秒表源程序
秒表源程序
一、秒表(XX.X秒)设计源程序
顶层设计源文件:
--inputclock1000hz
libraryIEEE;
useIEEE.std_logic_1164.all;
entitystopwatcis
port(CLK1khz:
inSTD_LOGIC;
RESET:
inSTD_LOGIC;
STRTSTOP:
inSTD_LOGIC;
LEDOUT:
outSTD_LOGIC_VECTOR(6downto0);
L00:
bufferSTD_LOGIC;--buffer
L11:
bufferSTD_LOGIC;--buffer
L22:
bufferSTD_LOGIC;--buffer
CKDSP:
INSTD_LOGIC);
endstopwatc;
architectureinsideofstopwatcis
--------------------------------------------------------
--LogiBLOXCOUNTERModule"cnt10"
--CreatedbyLogiBLOXversionD.19
--onSatMar1711:
26:
042001
--Attributes
--MODTYPE=COUNTER
--BUS_WIDTH=10
--STYLE=MAX_SPEED
--OPTYPE=UP
--ENCODING=ONE_HOT
--ASYNC_VAL=0000000001
------------------------------------------------------
----------------------------------------------------
--ComponentDeclaration
----------------------------------------------------
componentcnt10
PORT(
CLOCK:
INstd_logic;
ASYNC_CTRL:
INstd_logic;
TERM_CNT:
OUTstd_logic);
endcomponent;
------------------------------------------------------
--LogiBLOXCOUNTERModule"cnt102"
--CreatedbyLogiBLOXversionD.19
--onSatMar1712:
41:
402001
--Attributes
--MODTYPE=COUNTER
--BUS_WIDTH=10
--STYLE=MAX_SPEED
--OPTYPE=UP
--ENCODING=ONE_HOT
--ASYNC_VAL=0000000001
------------------------------------------------------
----------------------------------------------------
--ComponentDeclaration
----------------------------------------------------
componentcnt102
PORT(
CLOCK:
INstd_logic;
ASYNC_CTRL:
INstd_logic;
TERM_CNT:
OUTstd_logic);
endcomponent;
componentstatmach
port(CLK:
inSTD_LOGIC;
RESET:
inSTD_LOGIC;
STRTSTOP:
inSTD_LOGIC;
CLKEN:
outSTD_LOGIC;
RST:
outSTD_LOGIC);
endcomponent;
--PlacetheLogibloxComponentDeclarationforTenthshere
------------------------------------------------------
--LogiBLOXCOUNTERModule"Tenths"
--CreatedbyLogiBLOXversionD.19
--onTueMar0616:
31:
592001
--Attributes
--MODTYPE=COUNTER
--BUS_WIDTH=10
--STYLE=MAX_SPEED
--OPTYPE=UP
--ENCODING=ONE_HOT
--ASYNC_VAL=0000000001
------------------------------------------------------
----------------------------------------------------
--ComponentDeclaration
----------------------------------------------------
componentTenths
PORT(
CLK_EN:
INstd_logic;
CLOCK:
INstd_logic;
ASYNC_CTRL:
INstd_logic;
Q_OUT:
OUTstd_logic_vector(9DOWNTO0);
TERM_CNT:
OUTstd_logic);
endcomponent;
componentcnt60
port(CE:
inSTD_LOGIC;
CLK:
inSTD_LOGIC;
CLR:
inSTD_LOGIC;
LSBSEC:
outSTD_LOGIC_VECTOR(3downto0);
MSBSEC:
outSTD_LOGIC_VECTOR(3downto0));
endcomponent;
componenthex2led
port(HEX:
inSTD_LOGIC_VECTOR(3downto0);
LED:
outSTD_LOGIC_VECTOR(6downto0));
endcomponent;
componentcnt3
port(
clk:
inSTD_LOGIC;
clr:
inSTD_LOGIC;
q:
BUFFERSTD_LOGIC_VECTOR(2downto0)
);
endcomponent;
componentmux4
port(
in0:
inSTD_LOGIC_VECTOR(3downto0);
in1:
inSTD_LOGIC_VECTOR(3downto0);
in2:
inSTD_LOGIC_VECTOR(3downto0);
muxout:
outSTD_LOGIC_VECTOR(3downto0);
a:
inSTD_LOGIC;
b:
inSTD_LOGIC
);
endcomponent;
componentencode
port(
a:
inSTD_LOGIC_VECTOR(9downto0);
b:
outSTD_LOGIC_VECTOR(3downto0)
);
endcomponent;
signalreset1,clk2,clk,strtstopinv:
STD_LOGIC;
signalclkenable:
STD_LOGIC;
signalrstint:
STD_LOGIC;
signalxcountout:
STD_LOGIC_VECTOR(9downto0);
signalxtermcnt:
STD_LOGIC;
signalcnt60enable:
STD_LOGIC;
signallsbcnt:
STD_LOGIC_VECTOR(3downto0);
signalmsbcnt:
STD_LOGIC_VECTOR(3downto0);
signalbitms,hexin:
STD_LOGIC_VECTOR(3downto0);
begin
--inputclock1000hz
clk100hz:
cnt10portmap
(CLOCK=>clk1khz,
ASYNC_CTRL=>reset1,
TERM_CNT=>clk2);
----------------------------------------------------
--ComponentInstantiation
----------------------------------------------------
clk10hz:
cnt102portmap
(CLOCK=>clk2,
ASYNC_CTRL=>reset1,
TERM_CNT=>clk);
MACHINE:
statmachportmap(CLK=>CLK,
RESET=>RESET1,
STRTSTOP=>strtstopinv,
CLKEN=>clkenable,
RST=>rstint);
--PlacetheLogibloxComponentInstantiationforTenthshere
----------------------------------------------------
--ComponentInstantiation
----------------------------------------------------
XCOUNTER:
Tenthsportmap
(CLK_EN=>CLKENABLe,
CLOCK=>clk,
ASYNC_CTRL=>rstint,
Q_OUT=>xcountout,
TERM_CNT=>xtermcnt);
sixty:
cnt60portmap(CE=>cnt60enable,
CLK=>CLK,
CLR=>rstint,
LSBSEC=>lsbcnt,
MSBSEC=>msbcnt);
led:
hex2ledportmap(HEX=>HEXIN,
LED=>LEDOUT);
U1:
ENCODEPORTMAP(A=>XCOUNTOUT,B=>BITMS);
U2:
MUX4PORTMAP(IN0=>MSBCNT,IN1=>LSBCNT,IN2=>BITMS,MUXOUT=>HEXIN,A=>L00,B=>L11);
U3:
CNT3PORTMAP(CLR=>RSTINT,CLK=>CKDSP,Q(0)=>L00,Q
(1)=>L11,Q
(2)=>L22);
cnt60enable<=xtermcntandclkenable;
strtstopinv<=not(STRTSTOP);
RESET1<=NOT(RESET);
endinside;
底层设计源文件statmach
这是一个Moore状态机设计,目的是将机械按键形成的抖动去掉,将由按钮形成的复位信号整理成一个时钟周期长的信号,下面分别是状态机的2进程、3进程和单进程描述方式,请同学们仔细阅读。
(1)2进程描述方式:
libraryIEEE;
useIEEE.std_logic_1164.all;
entitystatmachis
port(CLK:
inSTD_LOGIC;
RESET:
inSTD_LOGIC;
STRTSTOP:
inSTD_LOGIC;
CLKEN:
outSTD_LOGIC;
RST:
outSTD_LOGIC);
endstatmach;
ARCHITECTUREinside_2OFstatmachIS
typestmchine_stateis(clear,zero,start,counting,stop,stopped);
signalcurrent_state:
stmchine_state;
signalnext_state:
stmchine_state;
begin
process(STRTSTOP,current_state)--这是次态和输出组合逻辑描述
begin
casecurrent_stateis
whenclear=>
next_state<=zero;
CLKEN<='0';
RST<='1';
whenzero=>
if(STRTSTOP='0')then
next_state<=zero;
elsif(STRTSTOP='1')then
next_state<=start;
endif;
CLKEN<='0';
RST<='0';
whenstart=>
if(STRTSTOP='0')then
next_state<=counting;
elsif(STRTSTOP='1')then
next_state<=start;
endif;
CLKEN<='1';
RST<='0';
whencounting=>
if(STRTSTOP='0')then
next_state<=counting;
elsif(STRTSTOP='1')then
next_state<=stop;
endif;
CLKEN<='1';
RST<='0';
whenstop=>
if(STRTSTOP='0')then
next_state<=stopped;
elsif(STRTSTOP='1')then
next_state<=stop;
endif;
CLKEN<='0';
RST<='0';
whenstopped=>
if(STRTSTOP='0')then
next_state<=stopped;
elsif(STRTSTOP='1')then
next_state<=start;
endif;
CLKEN<='0';
RST<='0';
endcase;
endprocess;
process(RESET,CLK)--这是触发器描述
begin
if(RESET='1')then
current_state<=clear;
elsif(CLK'eventandCLK='1')then
current_state<=next_state;
endif;
endprocess;
endinside_2;
(2)3进程描述方式:
libraryIEEE;
useIEEE.std_logic_1164.all;
entitystatmachis
port(CLK:
inSTD_LOGIC;
RESET:
inSTD_LOGIC;
STRTSTOP:
inSTD_LOGIC;
CLKEN:
outSTD_LOGIC;
RST:
outSTD_LOGIC);
endstatmach;
architectureinside_3ofstatmachis
typestmchine_stateis(clear,zero,start,
counting,stop,stopped);
signalcurrent_state:
stmchine_state;
signalnext_state:
stmchine_state;
begin
process(STRTSTOP,current_state)--这是次态组合逻辑
begin
casecurrent_stateis
whenclear=>
next_state<=zero;
whenzero=>
if(STRTSTOP='0')then
next_state<=zero;
elsif(STRTSTOP='1')then
next_state<=start;
endif;
whenstart=>
if(STRTSTOP='0')then
next_state<=counting;
elsif(STRTSTOP='1')then
next_state<=start;
endif;
whencounting=>
if(STRTSTOP='0')then
next_state<=counting;
elsif(STRTSTOP='1')then
next_state<=stop;
endif;
whenstop=>
if(STRTSTOP='0')then
next_state<=stopped;
elsif(STRTSTOP='1')then
next_state<=stop;
endif;
whenstopped=>
if(STRTSTOP='0')then
next_state<=stopped;
elsif(STRTSTOP='1')then
next_state<=start;
endif;
endcase;
endprocess;
process(STRTSTOP,current_state)--这是输出组合逻辑
begin
casecurrent_stateis
whenclear=>
CLKEN<='0';
RST<='1';
whenzero=>
CLKEN<='0';
RST<='0';
whenstart=>
CLKEN<='1';
RST<='0';
whencounting=>
CLKEN<='1';
RST<='0';
whenstop=>
CLKEN<='0';
RST<='0';
whenstopped=>
CLKEN<='0';
RST<='0';
endcase;
endprocess;
process(RESET,CLK)--这是触发器描述
begin
if(RESET='1')then
current_state<=clear;
elsif(CLK'eventandCLK='1')then
current_state<=next_state;
endif;
endprocess;
ENDinside_3;
(3)单进程描述方式:
libraryIEEE;
useIEEE.std_logic_1164.all;
entitystatmachis
port(CLK:
inSTD_LOGIC;
RESET:
inSTD_LOGIC;
STRTSTOP:
inSTD_LOGIC;
CLKEN:
outSTD_LOGIC;
RST:
outSTD_LOGIC);
endstatmach;
architectureinside_1OFstatmachIS
typestmchine_stateis(clear,zero,start,
counting,stop,stopped);
signalcurrent_state:
stmchine_state;
BEGIN
PROCESS(clk,reset)--所有逻辑全部在这一个进程中描述,
--综合出的电路输出信是被触发器锁存的
--只需说明一个内部的现态信号即可
IF(reset='1')THEN
current_state<=clear;
CLKEN<='0';
RST<='1';
elsif(CLK'eventandCLK='1')then
casecurrent_stateis
whenclear=>
current_state<=zero;
CLKEN<='0';
RST<='1';
whenzero=>
if(STRTSTOP='0')then
current_state<=zero;
elsif(STRTSTOP='1')then
current_state<=start;
endif;
CLKEN<='0';
RST<='0';
whenstart=>
if(STRTSTOP='0')then
current_state<=counting;
elsif(STRTSTOP='1')then
current_state<=start;
endif;
CLKEN<='1';
RST<='0';
whencounting=>
if(STRTSTOP='0')then
current_state<=counting;
elsif(STRTSTOP='1')then
current_state<=stop;
endif;
CLKEN<='1';
RST<='0';
whenstop=>
if(STRTSTOP='0')then
current_state<=stopped;
elsif(STRTSTOP='1')then
current_state<=stop;
endif;
CLKEN<='0';
RST<='0';
whenstopped=>
if(STRTSTOP='0')then
current_state<=stopped;
elsif(STRTSTOP='1')then
current_state<=start;
endif;
CLKEN<='0';
RST<='0';
endcase;
endprocess;
endinside_1;
底层设计源文件mux4
libraryIEEE;
useIEEE.std_logic_1
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