实验六.docx
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实验六.docx
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实验六
实验六交通信号灯控制器的设计
一、实验目的
1、熟悉QuartusⅡ/ISESuite/ispLEVER软件的基本使用方法。
2、熟悉GW48-CK或其他EDA实验开发系统的基本使用方法。
3、学习VHDL基本逻辑电路和状态机电路的综合设计应用。
二、实验条件
1、开发软件:
QuartusⅡ8.1。
2、实验设备:
DVCC-EJHEDA技术实验及开发系统。
3、拟用芯片:
EPM7128SLC84-15或EP1K100QC208-3。
三、实验内容
设计并调试好一个由主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器,具体要求如下:
(1)主、支干道各设有一个绿、黄、红指示灯,两个显示数码管。
(2)主干道处于常允许通行状态,而支干道有车来才允许通行。
当主干道允许通行亮绿灯时,支干道亮红灯,而支干道允许亮绿灯时,主干道亮红灯。
(3)当主、支干道均有车时,两者交替允许通行,主干道每次放行45s,支干道每次放行25s,在每次由亮绿灯变成亮红灯的转换过程中,要亮5s的黄灯作为过渡,并进行减计时显示。
整个设计及包括计时信号发生器、交通灯控制器以及译码显示电路的设计。
用GW48-CK或其他EDA实验开发系统(事先应选定拟采用的实验芯片的型号)进行硬件验证。
四、实验设计
1、系统原理图如下所示。
图 交通控制器的内部逻辑结构原理图
2、VHDL源程序
1、交通灯控制模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYJTDKZIS
PORT(CLK,SM,SB:
INSTD_LOGIC;
MR,MY,MG,BR,BY,BG:
OUTSTD_LOGIC);
ENDENTITYJTDKZ;
ARCHITECTUREARTOFJTDKZIS
TYPESTATE_TYPEIS(A,B,C,D);
SIGNALSTATE:
STATE_TYPE;
BEGIN
CNT:
PROCESS(CLK)IS
VARIABLES:
INTEGERRANGE0TO45;
VARIABLECLR,EN:
BIT;
BEGIN
IF(CLK'EVENTANDCLK='1')THEN
IFCLR='0'THENS:
=0;
ELSIFEN='0'THENS:
=S;
ELSES:
=S+1;
ENDIF;
CASESTATEIS
WHENA=>MR<='0';MY<='0';MG<='1';
BR<='1';BY<='0';BG<='0';
IF(SBANDSM)='1'THEN
IFS=45THEN
STATE<=B;CLR:
='0';EN:
='0';
ELSE
STATE<=A;CLR:
='1';EN:
='1';
ENDIF;
ELSIF(SBAND(NOTSM))='1'THEN
STATE<=B;CLR:
='0';EN:
='0';
ELSE
STATE<=A;CLR:
='1';EN:
='1';
ENDIF;
WHENB=>MR<='0';MY<='1';MG<='0';
BR<='1';BY<='0';BG<='0';
IFS=5THEN
STATE<=C;CLR:
='0';EN:
='0';
ELSE
STATE<=B;CLR:
='1';EN:
='1';
ENDIF;
WHENC=>MR<='1';MY<='0';MG<='0';
BR<='0';BY<='0';BG<='1';
IF(SMANDSB)='1'THEN
IFS=25THEN
STATE<=D;CLR:
='0';EN:
='0';
ELSE
STATE<=C;CLR:
='1';EN:
='1';
ENDIF;
ELSIFSB='0'THEN
STATE<=D;CLR:
='0';EN:
='0';
ELSE
STATE<=C;CLR:
='1';EN:
='1';
ENDIF;
WHEND=>MR<='1';MY<='0';MG<='0';
BR<='0';BY<='1';BG<='0';
IFS=5THEN
STATE<=A;CLR:
='0';EN:
='0';
ELSE
STATE<=D;CLR:
='1';EN:
='1';
ENDIF;
ENDCASE;
ENDIF;
ENDPROCESSCNT;
ENDARCHITECTUREART;
2、45s定时模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT45SIS
PORT(SB,CLK,EN45:
INSTD_LOGIC;
DOUT45M,DOUT45B:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITYCNT45S;
ARCHITECTUREARTOFCNT45SIS
SIGNALCNT6B:
STD_LOGIC_VECTOR(5DOWNTO0);
BEGIN
PROCESS(SB,CLK,EN45)IS
BEGIN
IFSB='0'THENCNT6B<=CNT6B-1;
ELSIF(CLK'EVENTANDCLK='1')THEN
IFEN45='1'THENCNT6B<=CNT6B+1;
ELSIFEN45='0'THENCNT6B<=CNT6B-CNT6B-1;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(CNT6B)IS
BEGIN
CASECNT6BIS
WHEN"000000"=>DOUT45M<="01000101";DOUT45B<="01010000";
WHEN"000001"=>DOUT45M<="01000100";DOUT45B<="01001001";
WHEN"000010"=>DOUT45M<="01000011";DOUT45B<="01001000";
WHEN"000011"=>DOUT45M<="01000010";DOUT45B<="01000111";
WHEN"000100"=>DOUT45M<="01000001";DOUT45B<="01000110";
WHEN"000101"=>DOUT45M<="01000000";DOUT45B<="01000101";
WHEN"000110"=>DOUT45M<="00111001";DOUT45B<="01000100";
WHEN"000111"=>DOUT45M<="00111000";DOUT45B<="01000011";
WHEN"001000"=>DOUT45M<="00110111";DOUT45B<="01000010";
WHEN"001001"=>DOUT45M<="00110110";DOUT45B<="01000001";
WHEN"001010"=>DOUT45M<="00110101";DOUT45B<="01000000";
WHEN"001011"=>DOUT45M<="00110100";DOUT45B<="00111001";
WHEN"001100"=>DOUT45M<="00110011";DOUT45B<="00111000";
WHEN"001101"=>DOUT45M<="00110010";DOUT45B<="00110111";
WHEN"001110"=>DOUT45M<="00110001";DOUT45B<="00110110";
WHEN"001111"=>DOUT45M<="00110000";DOUT45B<="00110101";
WHEN"010000"=>DOUT45M<="00101001";DOUT45B<="00110100";
WHEN"010001"=>DOUT45M<="00101000";DOUT45B<="00110011";
WHEN"010010"=>DOUT45M<="00100111";DOUT45B<="00110010";
WHEN"010011"=>DOUT45M<="00100110";DOUT45B<="00110001";
WHEN"010100"=>DOUT45M<="00100101";DOUT45B<="00110000";
WHEN"010101"=>DOUT45M<="00100100";DOUT45B<="00101001";
WHEN"010110"=>DOUT45M<="00100011";DOUT45B<="00101000";
WHEN"010111"=>DOUT45M<="00100010";DOUT45B<="00100111";
WHEN"011000"=>DOUT45M<="00100001";DOUT45B<="00100110";
WHEN"011001"=>DOUT45M<="00100000";DOUT45B<="00100101";
WHEN"011010"=>DOUT45M<="00011001";DOUT45B<="00100100";
WHEN"011011"=>DOUT45M<="00011000";DOUT45B<="00100011";
WHEN"011100"=>DOUT45M<="00010111";DOUT45B<="00100010";
WHEN"011101"=>DOUT45M<="00010110";DOUT45B<="00100001";
WHEN"011110"=>DOUT45M<="00010101";DOUT45B<="00100000";
WHEN"011111"=>DOUT45M<="00010100";DOUT45B<="00011001";
WHEN"100000"=>DOUT45M<="00010011";DOUT45B<="00011000";
WHEN"100001"=>DOUT45M<="00010010";DOUT45B<="00010111";
WHEN"100010"=>DOUT45M<="00010001";DOUT45B<="00010110";
WHEN"100011"=>DOUT45M<="00010000";DOUT45B<="00010101";
WHEN"100100"=>DOUT45M<="00001001";DOUT45B<="00010100";
WHEN"100101"=>DOUT45M<="00001000";DOUT45B<="00010011";
WHEN"100110"=>DOUT45M<="00000111";DOUT45B<="00010010";
WHEN"100111"=>DOUT45M<="00000110";DOUT45B<="00010001";
WHEN"101000"=>DOUT45M<="00000111";DOUT45B<="00010000";
WHEN"101001"=>DOUT45M<="00000100";DOUT45B<="00001001";
WHEN"101010"=>DOUT45M<="00000011";DOUT45B<="00001000";
WHEN"101011"=>DOUT45M<="00000010";DOUT45B<="00000111";
WHEN"101100"=>DOUT45M<="00000001";DOUT45B<="00000110";
WHENOTHERS=>DOUT45M<="00000000";DOUT45B<="00000000";
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREART;
3、25s定时模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT25SIS
PORT(SB,SM,CLK,EN25:
INSTD_LOGIC;
DOUT25M,DOUT25B:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITYCNT25S;
ARCHITECTUREARTOFCNT25SIS
SIGNALCNT5B:
STD_LOGIC_VECTOR(4DOWNTO0);
BEGIN
PROCESS(SB,SM,CLK,EN25)IS
BEGIN
IFSB='0'ORSM='0'THENCNT5B<=CNT5B-1;
ELSIF(CLK'EVENTANDCLK='1')THEN
IFEN25='1'THENCNT5B<=CNT5B+1;
ELSIFEN25='0'THENCNT5B<=CNT5B-CNT5B-1;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(CNT5B)IS
BEGIN
CASECNT5BIS
WHEN"00000"=>DOUT25B<="00100101";DOUT25M<="00110000";
WHEN"00001"=>DOUT25B<="00100100";DOUT25M<="00101001";
WHEN"00010"=>DOUT25B<="00100011";DOUT25M<="00101000";
WHEN"00011"=>DOUT25B<="00100010";DOUT25M<="00100111";
WHEN"00100"=>DOUT25B<="00100001";DOUT25M<="00100110";
WHEN"00101"=>DOUT25B<="00100000";DOUT25M<="00100101";
WHEN"00110"=>DOUT25B<="00011001";DOUT25M<="00100100";
WHEN"00111"=>DOUT25B<="00011000";DOUT25M<="00100011";
WHEN"01000"=>DOUT25B<="00010111";DOUT25M<="00100010";
WHEN"01001"=>DOUT25B<="00010110";DOUT25M<="00100001";
WHEN"01010"=>DOUT25B<="00010101";DOUT25M<="00100000";
WHEN"01011"=>DOUT25B<="00010100";DOUT25M<="00011001";
WHEN"01100"=>DOUT25B<="00010011";DOUT25M<="00011000";
WHEN"01101"=>DOUT25B<="00010010";DOUT25M<="00010111";
WHEN"01110"=>DOUT25B<="00010001";DOUT25M<="00010110";
WHEN"01111"=>DOUT25B<="00010000";DOUT25M<="00010101";
WHEN"10000"=>DOUT25B<="00001001";DOUT25M<="00010100";
WHEN"10001"=>DOUT25B<="00001000";DOUT25M<="00010011";
WHEN"10010"=>DOUT25B<="00000111";DOUT25M<="00010010";
WHEN"10011"=>DOUT25B<="00000110";DOUT25M<="00010001";
WHEN"10100"=>DOUT25B<="00000101";DOUT25M<="00010000";
WHEN"10101"=>DOUT25B<="00000100";DOUT25M<="00001001";
WHEN"10110"=>DOUT25B<="00000011";DOUT25M<="00001000";
WHEN"10111"=>DOUT25B<="00000010";DOUT25M<="00000111";
WHEN"11000"=>DOUT25B<="00000001";DOUT25M<="00000110";
WHENOTHERS=>DOUT25B<="00000000";DOUT25M<="00000000";
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREART;
4、05s定时模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT05SIS
PORT(CLK,EN05M,EN05B:
INSTD_LOGIC;
DOUT5:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITYCNT05S;
ARCHITECTUREARTOFCNT05SIS
SIGNALCNT3B:
STD_LOGIC_VECTOR(2DOWNTO0);
BEGIN
PROCESS(CLK,EN05M,EN05B)IS
BEGIN
IF(CLK'EVENTANDCLK='1')THEN
IFEN05M='1'OREN05B='1'THEN
CNT3B<=CNT3B+1;
ELSE
CNT3B<="000";
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(CNT3B)IS
BEGIN
CASECNT3BIS
WHEN"000"=>DOUT5<="00000101";
WHEN"001"=>DOUT5<="00000100";
WHEN"010"=>DOUT5<="00000011";
WHEN"011"=>DOUT5<="00000010";
WHEN"100"=>DOUT5<="00000001";
WHENOTHERS=>DOUT5<="00000000";
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREART;
5、显示器控制模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYXSKZIS
PORT(EN45,EN25,EN05M,EN05B:
INSTD_LOGIC;
AIN45M,AIN45B:
INSTD_LOGIC_VECTOR(7DOWNTO0);
AIN25M,AIN25B,AIN05:
INSTD_LOGIC_VECTOR(7DOWNTO0);
DOUTM,DOUTB:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITYXSKZ;
ARCHITECTUREARTOFXSKZIS
BEGIN
PROCESS(EN45,EN25,EN05M,EN05B)IS
BEGIN
IFEN45='1'THEN
DOUTM<=AIN45M(7DOWNTO0);DOUTB<=AIN45B(7DOWNTO0);
ELSIFEN05M='1'THEN
DOUTM<=AIN05(7DOWNTO0);DOUTB<=AIN05(7DOWNTO0);
ELSIFEN25='1'THEN
DOUTM<=AIN25M(7DOWNTO0);DOUTB<=AIN25B(7DOWNTO0);
ELSIFEN05B='1'THEN
DOUTM<=AIN05(7DOWNTO0);DOUTB<=AIN05(7DOWNTO0);
ENDIF;
ENDPROCESS;
ENDARCHITECTUREART;
3、仿真波形设置
(1)交通灯控制模块
图 交通灯控制模块仿真波形
(2)45s定时模块
图 45s定时模块仿真波形
(3)25s定时模块
图 25s定时模块模块仿真波形
(4)5s定时模块
图 5s定时模块仿真波形
(5)显示控制模块
图 显示控制模块模块仿真波形
4、芯片选择及引脚分配
系统顶层设计模块clock选用EP1K100QC208-3芯片。
芯片选择过程如图1.8所示,根据实验系统有关输入输出资源情况进行引脚锁定,并将闲置引脚设定为三态门状态。
引脚连接如表1-1,锁定过程如图1.10所示。
表1-1 引脚对应表
引脚名
引脚号
引脚名
引脚号
引脚名
引脚号
EN05B
7
AIN25M[7]
38
AIN45M[3]
127
EN05M
8
AIN25M[6]
39
AIN45M[2]
128
EN25
9
AIN25M[5]
40
AIN45M[1]
131
EN45
11
AIN25M[4]
41
AIN45M[0]
132
AIN05[7]
12
AIN25M[3]
44
DOUTB[7]
133
AIN05[6]
13
AIN25M[2]
45
DOUTB[6]
134
AIN05[5]
14
AIN25M[1]
46
DOUTB[5]
135
AIN05[4]
15
AIN25M[0]
47
DOUTB[4]
136
AIN05[3]
17
AIN45B[7]
111
DOUTB[3]
139
AIN05[2]
18
AIN45B[6]
112
DOUTB[2]
140
AIN05[1]
24
AIN45B[5]
113
DOUTB[1]
141
AIN05[0]
25
AIN45B[4]
114
DOUTB[0]
142
AIN25B[7]
26
AIN45B[3]
115
DOUTM[7]
143
AIN25B[6]
27
AIN45B[2]
116
DOUTM[6]
144
AIN25B[5]
28
AIN45B[1]
119
DOUTM[5]
147
AIN25B[4]
29
AIN45B[0]
120
DOUTM[4]
148
AIN25B[3]
30
AIN45M[7]
121
DOUTM[3]
149
AIN25B[2]
31
AIN45M[6]
122
DOUTM[2]
150
AIN25B[1]
36
AIN45M[5]
125
DOUTM[1]
187
AIN25B
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