eda报告.docx
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eda报告.docx
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eda报告
武汉大学珞珈学院
E
D
A
技
术
实
验
20130803081
曾德胜
实验一:
EDA电路仿真
一、实验目的:
掌握利用原理图输入法设计简单组合电路的方法,掌握MAX+plusII的层次化设计方法。
通过一个4位全加器的设计,熟悉用EDA软件进行电路设计的详细流程。
二、实验原理:
熟悉QuartusII软件界面,掌握利用原理图进行电路模块设计的方法。
QuartusII设计流程见教材第五章:
QuartusII应用向导。
3、实验内容:
实验二:
与门、3-8译码器
1、实验目的:
(1)编辑与非门的程序及仿真波形;
(2)编辑3-8译码器的程序及仿真波形。
2、实验原理:
(1)利用与逻辑门电路的原理编写与门的程序;
(2)3-8译码器利用3输入8输出的译码器将无法识别的信号译为计算机可识别的信号,根据3-8译码器的功能原理编写其程序。
3、实验内容:
(1)点击File→Newprojectwizard...→选择保存途径→修改工程名为ch2→Next→Finish;
(2)点击File→New→DesignFiles→VHDLFile;
(3)与门程序:
(4)3-8译码器程序:
4、实验结果:
(1)与门仿真结果:
(2)3-8译码器仿真结果:
实验三:
元件编程下载
1、实验目的:
(1)使用VHDL硬件设计两个基本的逻辑电路;
(2)熟悉与门逻辑电路,3-8译码器电路。
2、实验原理:
设计一个与门电路,一个3-8译码器电路,实现其功能。
3、实验内容:
(1)与门程序:
(2)3-8译码器程序:
实验四:
三进制计数器输出led显示
1、实验目的:
(1)通过4选1数据选择器输出显示实验的基本操作,用来进一步掌握三进制计数器输出显示的具体操作;
(2)掌握VHDL语言程序文件在QuartusII6.0软件中“多合一”的操作方法。
2、实验程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityclk_div1000is
port(clk:
instd_logic;
clk_div:
outstd_logic);
endclk_div1000;
architecturertlofclk_div1000is
signalq_tmp:
integerrange0to59999999;
begin
process(clk)
begin
if(clk'eventandclk='1')then
if(q_tmp=59999999)then
q_tmp<=0;
else
q_tmp<=q_tmp+1;
endif;
endif;
endprocess;
process(clk)
begin
if(clk'eventandclk='1')then
if(q_tmp=59999999)then
clk_div<='1';
else
clk_div<='0';
endif;
endif;
endprocess;
endrtl;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount3is
port(
enable:
instd_logic;
clk:
instd_logic;
q:
outstd_logic_vector(1downto0));
endcount3;
architecturertlofcount3is
signalq_tmp:
std_logic_vector(1downto0);
begin
process(clk)
begin
if(clk'eventandclk='1')then
if(enable='1')then
if(q_tmp="10")then
q_tmp<=(others=>'0');
else
q_tmp<=q_tmp+1;
endif;
endif;
endif;
q<=q_tmp;
endprocess;
endrtl;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitych30is
port(clk:
instd_logic;
enable:
instd_logic;
q:
outstd_logic_vector(1downto0));
end;
architectureart1ofch30is
componentclk_div1000
port(clk:
instd_logic;
clk_div:
outstd_logic);
endcomponent;
componentcount3
port(
enable:
instd_logic;
clk:
instd_logic;
q:
outstd_logic_vector(1downto0));
endcomponent;
signalx:
std_logic;
begin
u0:
clk_div1000portmap(clk,x);
u1:
count3portmap(enable,x,q);
end;
3、管脚配置:
4、下载及扩展电路连接:
实验四:
三进制计数器输出数码管显示
一、实验目的:
(1)通过4选1数据选择器输出显示实验的基本操作,用来进一步掌握三进制计数器输出显示的具体操作;
(2)掌握VHDL语言程序文件在QuartusII6.0软件中“多合一”的操作方法;
(3)将三进制计数器led显示转换为数码管显示,并观察数码管亮灭。
2、实验程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount3is
port(
enable:
instd_logic;
clk:
instd_logic;
q:
outstd_logic_vector(1downto0)
);
endcount3;
architecturert1ofcount3is
signalq_temp:
std_logic_vector(1downto0);
begin
process(clk)
begin
if(clk'eventandclk='1')then
if(enable='1')then
if(q_temp="10")then
q_temp<=(others=>'0');
else
q_temp<=q_temp+1;
endif;
endif;
endif;
q<=q_temp;
endprocess;
endrt1;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityclk_divis
port(clk:
instd_logic;
clk_div:
outstd_logic);
endclk_div;
architecturert1ofclk_divis
signalq_temp:
integerrange0to59999999;
begin
process(clk)
begin
if(clk'eventandclk='1')then
if(q_temp=59999999)then
q_temp<=0;
else
q_temp<=q_temp+1;
endif;
endif;
endprocess;
process(clk)
begin
if(clk'eventandclk='1')then
if(q_temp=59999999)then
clk_div<='1';
else
clk_div<='0';
endif;
endif;
endprocess;
endrt1;
libraryieee;
useieee.std_logic_1164.all;
entityseg7is
port(q:
instd_logic_vector(1downto0);
segment:
outstd_logic_vector(0to7));
endseg7;
architecturert1ofseg7is
begin
process(q)
begin
caseqis
when"00"=>segment<="11000000";
when"01"=>segment<="11111001";
when"10"=>segment<="10100100";
whenothers=>segment<="XXXXXXXX";
endcase;
endprocess;
endrt1;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitych30is
port(clk:
instd_logic;
enable:
instd_logic;
segment:
outstd_logic_vector(0to7)
);
endch30;
architecturert1ofch30is
componentclk_div
port(clk:
instd_logic;
clk_div:
outstd_logic);
endcomponent;
componentcount3
port(enable:
instd_logic;
clk:
instd_logic;
q:
outstd_logic_vector(1downto0)
);
endcomponent;
componentseg7
port(q:
instd_logic_vector(1downto0);
segment:
outstd_logic_vector(0to7)
);
endcomponent;
signalx:
std_logic;
signalh:
std_logic_vector(1downto0);
begin
U0:
clk_divportmap(clk,x);
U1:
count3portmap(enable,x,h);
U2:
seg7portmap(h,segment);
end;
三、管脚配置:
四、下载及扩展电路连接:
实验五:
24进制计数器输出数码管显示
一、实验目的:
(1)通过4选1数据选择器输出显示实验的基本操作,用来进一步掌握三进制计数器输出显示的具体操作;
(2)掌握VHDL语言程序文件在QuartusII6.0软件中“多合一”的操作方法;
(3)将24进制计数器用数码管显示,并观察数码管亮灭。
二、实验程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityclk_divis
port(clk:
instd_logic;
clk_div:
outstd_logic);
endclk_div;
architecturert1ofclk_divis
signalq_temp:
integerrange0to59999999;
begin
process(clk)
begin
if(clk'eventandclk='1')then
if(q_temp=59999999)then
q_temp<=0;
else
q_temp<=q_temp+1;
endif;
endif;
endprocess;
process(clk)
begin
if(clk'eventandclk='1')then
if(q_temp=59999999)then
clk_div<='1';
else
clk_div<='0';
endif;
endif;
endprocess;
endrt1;
libraryieee;
useieee.std_logic_1164.all;
entityseg7is
port(q:
instd_logic_vector(3downto0);
segment:
outstd_logic_vector(0to7));
endseg7;
architecturert1ofseg7is
begin
process(q)
begin
caseqis
when"0000"=>segment<="11000000";
when"0001"=>segment<="11111001";
when"0010"=>segment<="10100100";
when"0011"=>segment<="10110000";
when"0100"=>segment<="10011001";
when"0101"=>segment<="10010010";
when"0110"=>segment<="10000010";
when"0111"=>segment<="11011000";
when"1000"=>segment<="10000000";
when"1001"=>segment<="10010000";
whenothers=>segment<="XXXXXXXX";
endcase;
endprocess;
endrt1;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount24is
port(
enable:
instd_logic;
clk0:
instd_logic;
qh:
outstd_logic_vector(3downto0);
ql:
outstd_logic_vector(3downto0));
endcount24;
architecturert1ofcount24is
signalqh_temp,ql_temp:
std_logic_vector(3downto0);
begin
process(clk0)
begin
if(clk0'eventandclk0='1')then
if(enable='1')then
if(qh_temp="0010"andql_temp="0011")then
qh_temp<="0000";
ql_temp<="0000";
else
if(ql_temp="1001")then
ql_temp<="0000";
qh_temp<=qh_temp+1;
else
ql_temp<=ql_temp+1;
endif;
endif;
endif;
endif;
qh<=qh_temp;
ql<=ql_temp;
endprocess;
endrt1;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitych30is
port(clk:
instd_logic;
enable:
instd_logic;
segment1:
outstd_logic_vector(0to7);
segment2:
outstd_logic_vector(0to7)
);
endch30;
architecturert1ofch30is
componentclk_div
port(clk:
instd_logic;
clk_div:
outstd_logic);
endcomponent;
componentcount24
port(
enable:
instd_logic;
clk0:
instd_logic;
qh:
outstd_logic_vector(3downto0);
ql:
outstd_logic_vector(3downto0));
endcomponent;
componentseg7
port(q:
instd_logic_vector(3downto0);
segment:
outstd_logic_vector(0to7));
endcomponent;
signalx:
std_logic;
signalqh:
std_logic_vector(3downto0);
signalql:
std_logic_vector(3downto0);
begin
U0:
clk_divportmap(clk,x);
U1:
count24portmap(enable,x,qh,ql);
U2:
seg7portmap(qh,segment1);
U3:
seg7portmap(ql,segment2);
end;
三、管脚配置:
四、下载及扩展电路连接:
实验六:
3081进制计数器输出数码管显示
一、实验目的:
(1)通过4选1数据选择器输出显示实验的基本操作,用来进一步掌握三进制计数器输出显示的具体操作;
(2)掌握VHDL语言程序文件在QuartusII6.0软件中“多合一”的操作方法;
(3)将24进制计数器用数码管显示,并观察数码管亮灭。
二、实验程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityclk_divis
port(clk:
instd_logic;
clk_div:
outstd_logic);
endclk_div;
architecturert1ofclk_divis
signalq_temp:
integerrange0to5999999;
begin
process(clk)
begin
if(clk'eventandclk='1')then
if(q_temp=5999999)then
q_temp<=0;
else
q_temp<=q_temp+1;
endif;
endif;
endprocess;
process(clk)
begin
if(clk'eventandclk='1')then
if(q_temp=5999999)then
clk_div<='1';
else
clk_div<='0';
endif;
endif;
endprocess;
endrt1;
libraryieee;
useieee.std_logic_1164.all;
entityseg7is
port(q:
instd_logic_vector(3downto0);
segment:
outstd_logic_vector(0to7));
endseg7;
architecturert1ofseg7is
begin
process(q)
begin
caseqis
when"0000"=>segment<="11000000";
when"0001"=>segment<="11111001";
when"0010"=>segment<="10100100";
when"0011"=>segment<="10110000";
when"0100"=>segment<="10011001";
when"0101"=>segment<="10010010";
when"0110"=>segment<="10000010";
when"0111"=>segment<="11011000";
when"1000"=>segment<="10000000";
when"1001"=>segment<="10010000";
whenothers=>segment<="XXXXXXXX";
endcase;
endprocess;
endrt1;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount3081is
port(
enable:
instd_logic;
clk0:
instd_logic;
q1:
outstd_logic_vector(3downto0);
q2:
outstd_logic_vector(3downto0);
q3:
outstd_logic_vector(3downto0);
q4:
outstd_logic_vector(3downto0));
endcount3081;
architecturert1ofcount3081is
signalq1_temp,q2_temp,q3_temp,q4_temp:
std_logic_vector(3downto0);
begin
process(clk0)
begin
if(clk0'eventandclk0=
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