VHDL报告.docx
- 文档编号:14778871
- 上传时间:2023-06-27
- 格式:DOCX
- 页数:13
- 大小:274.90KB
VHDL报告.docx
《VHDL报告.docx》由会员分享,可在线阅读,更多相关《VHDL报告.docx(13页珍藏版)》请在冰点文库上搜索。
VHDL报告
《EDA上机报告》
学院:
班级:
姓名:
学号:
2012年11月3日
试验一:
1.一位半加器(VHDL)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYhalf_add1is
PORT(
A,B:
INSTD_LOGIC;
C,S:
OUTSTD_LOGIC
);
ENDENTITYHALF_ADD1;
ARCHITECTUREARCHOFHALF_ADDER1IS
begin
S<=AxorB;
C<=AandB;
endarch;
2.半加器(原理图)
3.全加器(原理图)
4.全加器(例化语句)
libraryieee;
useieee.std_logic_1164.all;
entityfull_adder2is
port(
A,B,Cin:
instd_logic;
Sum,Cout:
outstd_logic
);
endfull_adder2;
architecturearchoffull_adderis
componenthalf_adder1
port(
A,B:
instd_logic;
S,C:
outstd_logic
);
endcomponent;
componentor22
port(
A,B:
instd_logic;
S,C:
outstd_logic
);
endcomponent;
signalx:
std_logic_vector(0to2);
begin
ul:
half_adder1portmap(A,B,X(0),x
(1));
u2:
half_adder1portmap(X(0),Cin,Sum,x
(2));
u3:
or22portmap(x
(1),x
(2),cout);
endarch;
或门
libraryieee;
useieee.std_logic_1164.all;
entityor22is
port(
A,B:
instd_logic;
C:
outstd_logic
);
endor22;
architecturearchofor22is
begin
C<=AorB;
endarch;
实验二:
四选一
1.IF….THEN….语句
libraryieee;
useieee.std_logic_1164.all;
entityMux4_11is
port(A,B,C,D:
instd_logic_vector(3downto0);
Sel:
instd_logic_vector(1downto0);
Y:
outstd_logic_vector(3downto0)
);
endMux4_11;
architecturearchofMux4_11is
begin
process(A,B,C,D,Sel)
begin
if(Sel="00")thenY<=A;
elsif(Sel="01")thenY<=B;
elsif(Sel="10")thenY<=C;
elsif(Sel="11")thenY<=D;
elseNULL;
endif;
endprocess;
endarch;
2.CASE….WHEN……语句
libraryieee;
useieee.std_logic_1164.all;
entityMux4_12is
port(A,B,C,D:
instd_logic_vector(3downto0);
Sel:
instd_logic_vector(1downto0);
Y:
outstd_logic_vector(3downto0)
);
endMux4_12;
architecturearchofMux4_12is
begin
process(A,B,C,D,Sel)
begin
caseSelis
when"00"=>Y<=A;
when"01"=>Y<=B;
when"10"=>Y<=C;
when"11"=>Y<=D;
whenothers=>NULL;
endcase;
endprocess;
endarch;
3.WHEN…..ElSE…..语句
libraryieee;
useieee.std_logic_1164.all;
entityMux4_13is
port(A,B,C,D:
instd_logic_vector(3downto0);
Sel:
instd_logic_vector(1downto0);
Y:
outstd_logic_vector(3downto0)
);
endMux4_13;
architecturearchofMux4_13is
begin
Y<=AwhenSel="00"else
BwhenSel="01"else
CwhenSel="10"else
DwhenSel="11"else
NULL;
endarch;
4.WITH….SELECT…..语句
libraryieee;
useieee.std_logic_1164.all;
entityMux4_14is
port(A,B,C,D:
instd_logic_vector(3downto0);
Sel:
instd_logic_vector(1downto0);
Y:
outstd_logic_vector(3downto0)
);
endMux4_14;
architecturearchofMux4_14is
begin
withSelselect
Y<=Awhen"00",
Bwhen"01",
Cwhen"10",
Dwhen"11",
"XXXX"whenothers;
endarch;
实验三:
计数器
1.触发器(同步清零)
libraryieee;
useieee.std_logic_1164.all;
entityDregis
port(
clk,D,Clr:
instd_logic;
Q:
bufferstd_logic
);
endDreg;
architecturearchofDregis
begin
process(clk,D,Clr)
begin
if(clk'eventandclk='1')then
if(clr='0')thenQ<='0';
elseQ<=D;
endif;
endif;
endprocess;
endarch;
2.计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt1is
port(
cp:
instd_logic;
Q:
bufferstd_logic_vector(3downto0)
);
endcnt1;
architecturearchofcnt1is
begin
process(cp)
begin
if(cp'eventandcp='1')thenQ<=q+1;
endif;
endprocess;
endarch;
3.可逆计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt2is
port(
cp,dir:
instd_logic;
Q:
bufferstd_logic_vector(3downto0)
);
endcnt2;
architecturearchofcnt2is
begin
process(cp,dir)
begin
if(cp'eventandcp='1')then
if(dir='0')thenQ<=q+1;
elseQ<=q-1;
endif;
endif;
endprocess;
endarch;
4.十六位计数器(异步清零,同步置数)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt16is
port(
cp,R,S:
instd_logic;
data:
instd_logic_vector(3downto0);
Co:
outstd_logic;
Q:
bufferstd_logic_vector(3downto0)
);
endcnt16;
architecturearchofcnt16is
begin
process(cp,R,S,data)
begin
if(R='0')thenQ<="0000";
elsif(cp'eventandcp='1')then
if(S='1')thenQ<=Data;
elseQ<=Q+1;
endif;
endif;
if(Q="1111")thenCo<='1';
elseco<='0';
endif;
endprocess;
endarch;
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- VHDL 报告