VHDL与数字集成电路设计VHDL7-1PPT文件格式下载.ppt
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- 上传时间:2023-05-13
- 格式:PPT
- 页数:39
- 大小:3.35MB
VHDL与数字集成电路设计VHDL7-1PPT文件格式下载.ppt
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"第七章:
@#@时间考虑,2,SynchronousTiming,3,LatchParameters,D,Clk,Q,D,Q,Clk,tc-q,thold,PWm,tsu,td-q,Delayscanbedifferentforrisingandfallingdatatransitions,T,4,RegisterParameters,D,Clk,Q,D,Q,Clk,tc-q,thold,T,tsu,Delayscanbedifferentforrisingandfallingdatatransitions,5,ClockUncertainties,Sourcesofclockuncertainty,6,ClockNonidealities,ClockskewSpatialvariationintemporallyequivalentclockedges;@#@deterministic+random,tSKClockjitterTemporalvariationsinconsecutiveedgesoftheclocksignal;@#@modulation+randomnoiseCycle-to-cycle(short-term)tJSLongtermtJLVariationofthepulsewidthImportantforlevelsensitiveclocking,7,ClockSkewandJitter,BothskewandjitteraffecttheeffectivecycletimeOnlyskewaffectstheracemargin,Clk,Clk,tSK,tJS,8,PositiveandNegativeSkew,9,PositiveSkew,Launchingedgearrivesbeforethereceivingedge,10,NegativeSkew,Receivingedgearrivesbeforethelaunchingedge,11,TimingConstraints,Minimumcycletime:
@#@T-=tc-q+tsu+tlogic,Worstcaseiswhenreceivingedgearrivesearly(positive),12,TimingConstraints,Holdtimeconstraint:
@#@t(c-q,cd)+t(logic,cd)thold+,WorstcaseiswhenreceivingedgearriveslateRacebetweendataandclock,13,ImpactofJitter,14,LongestLogicPathinEdge-TriggeredSystems,Clk,T,TSU,TClk-Q,TLM,Latestpointoflaunching,Earliestarrivalofnextcycle,TJI+d,15,ClockConstraintsinEdge-TriggeredSystems,Iflaunchingedgeislateandreceivingedgeisearly,thedatawillnotbetoolateif:
@#@,Minimumcycletimeisdeterminedbythemaximumdelaysthroughthelogic,Tc-q+TLM+TSUTTJI,1TJI,2-d,Tc-q+TLM+TSU+d+2TJIT,Skewcanbeeitherpositiveornegative,16,ShortestPath,Clk,TClk-Q,TLm,Earliestpointoflaunching,Datamustnotarrivebeforethistime,Clk,TH,Nominalclockedge,17,ClockConstraintsinEdge-TriggeredSystems,Minimumlogicdelay,Iflaunchingedgeisearlyandreceivingedgeislate:
@#@,Tc-q+TLMTJI,1TH+TJI,2+d,Tc-q+TLMTH+2TJI+d,18,ClockDistribution,Clockisdistributedinatree-likefashion,H-tree,19,MorerealisticH-tree,Restle98,20,TheGridSystem,Norc-matchingLargepower,21,21164Clocking,2phasesinglewireclock,distributedglobally2distributeddriverchannelsReducedRCdelay/skewImprovedthermaldistribution3.75nFclockload58cmfinaldriverwidthLocalinvertersforlatchingConditionalclocksincachestoreducepowerMorecomplexracecheckingDevicevariation,trise=0.35ns,tskew=150ps,tcycle=3.3ns,Clockwaveform,Locationofclockdriverondie,22,23,ClockSkewinAlphaProcessor,24,2Phase,withmultipleconditionalbufferedclocks2.8nFclockload40cmfinaldriverwidthLocalclockscanbegated“off”tosavepowerReducedload/skewReducedthermalissuesMultipleclockscomplicateracechecking,EV6(Alpha21264)Clocking600MHz0.35micronCMOS,Globalclockwaveform,25,SynchronousPipelinedDatapath,26,Self-TimedPipelinedDatapath,27,Hand-ShakingProtocol,TwoPhaseHandshake,28,EventLogicTheMuller-CElement,29,2-PhaseHandshakeProtocol,30,Example:
@#@Self-timedFIFO,31,PLL-BasedSynchronization,32,PLLBlockDiagram,33,PhaseDetector,Outputbeforefiltering,Transfercharacteristic,34,Phase-FrequencyDetector,35,PFDResponsetoFrequency,36,ChargePump,37,PLLSimulation,38,ClockGenerationusingDLLs,PD,CP,VCO,N,Phase-LockedLoop(VCO-Based),U,D,fO,fREF,Filter,39,DLL-BasedClockDistribution,";}
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- VHDL 数字 集成电路设计 VHDL7
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