diantikongzhiqi文档格式.docx
- 文档编号:5803863
- 上传时间:2023-05-05
- 格式:DOCX
- 页数:15
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diantikongzhiqi文档格式.docx
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caseledinis--Thesequenceis"
gfedcba"
when"
0000"
=>
ledout<
="
0111111"
;
--"
show0"
0001"
0000110"
show1"
0010"
1011011"
show2"
0011"
1001111"
show3"
0100"
1100110"
show4"
0101"
1101101"
show5"
0110"
1111101"
show6"
0111"
0000111"
show7"
1000"
1111111"
show8"
1001"
1101111"
show9"
1010"
1110111"
show10"
1011"
1111100"
show11"
1100"
0111001"
show12"
1101"
1011110"
show13"
1110"
1111001"
show14"
1111"
1110001"
show15"
whenothers=>
XXXXXXX"
--必须有,Hereitis'
X'
singlequote
endcase;
endprocess;
enda_led;
libraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.std_logic_arith.all;
useIEEE.std_logic_unsigned.all;
entitylift1is
port(
clk:
inSTD_LOGIC;
--2hz信号
upin:
--上升请求键
downin:
--下降请求键
st_ch:
--楼层选择键
close:
--提前关门键
delay:
--延时关门键
run_stop:
--电梯运行开关
lamp:
outSTD_LOGIC;
--运行或停止灯
run_waitdis:
outSTD_LOGIC_VECTOR(6downto0);
--运行或等待时间
st_outdis:
--电梯所在楼层指示
directdis:
outSTD_LOGIC_VECTOR(6downto0)--楼层选择指示
);
endlift1;
architecturelift1_archoflift1is
componentled1
endcomponent;
signalur,dr:
STD_LOGIC_VECTOR(6downto1);
signaldir,liftor:
integerrange0to5;
signalwai_t:
STD_LOGIC_VECTOR(2downto0);
signaldivide,hand,clkin:
STD_LOGIC;
signalladd:
STD_LOGIC_VECTOR(1downto0);
signalclosex,delayx:
signalrun_wait:
STD_LOGIC_VECTOR(3downto0);
signalst_out:
signaldirect:
direct<
='
0'
&
conv_std_logic_vector(dir,3)+1;
st_out<
conv_std_logic_vector(liftor,3)+1;
run_wait<
wai_t;
lamp<
=ladd
(1);
hand<
=wai_t
(2)and(notwai_t
(1))andwai_t(0);
closex<
=closeand(notladd
(1));
delayx<
=delayand(notladd
(1));
urun_wait:
led1portmap(run_wait,run_waitdis);
ust_out:
led1portmap(st_out,st_outdis);
udirect:
led1portmap(direct,directdis);
p0:
process(clk)
if(clk'
eventandclk='
1'
)then
clkin<
=notclkin;
endif;
endprocessp0;
p1:
process(clkin)
if(clkin'
eventandclkin='
divide<
=notdivide;
if(dir=5)then
dir<
=0;
else
=dir+1;
endprocessp1;
p2:
process(ur,dr,dir,upin,downin,st_ch,liftor,wai_t,run_stop,hand)
variablenum,t:
integerrange0to6;
num:
=liftor+1;
t:
if(run_stop='
if(((t>
num)and(st_ch='
))or(upin='
))then
casetis
when1=>
ur
(1)<
when2=>
ur
(2)<
when3=>
ur(3)<
when4=>
ur(4)<
when5=>
ur(5)<
when6=>
ur(6)<
Null;
elsif(hand='
)then
casenumis
if(((t<
))or(downin='
dr
(1)<
dr
(2)<
dr(3)<
dr(4)<
dr(5)<
dr(6)<
ur<
000000"
dr<
endprocessp2;
p3:
process(ur,dr,liftor,ladd,wai_t,run_stop)
if(wai_t="
110"
if((urordr)="
ladd
(1)<
caseliftoris
when0=>
if((ur
(1)ordr
(1))>
'
ladd<
11"
if((ur
(2)ordr
(2))>
elsif(((ladd(0)='
)and((ur(6downto3)ordr(6downto3))>
"
))or((ur
(1)ordr
(1))='
10"
if((ur(3)ordr(3))>
)and((ur(6downto4)ordr(6downto4))>
000"
))or((ur(2downto1)ordr(2downto1))="
00"
if((ur(4)ordr(4))>
)and((ur(6downto5)ordr(6downto5))>
))or((ur(3downto1)ordr(3downto1))="
if((ur(5)ordr(5))>
)and((ur(6)ordr(6))>
))or((ur(4downto1)ordr(4downto1))="
if((ur(6)ordr(6))>
whenothers=>
null;
endprocessp3;
p4:
process(divide,wai_t,ladd,closex,delayx)
if(divide'
eventanddivide='
orclosex='
wai_t<
if(delayx='
=wai_t-1;
010"
001"
if(ladd="
liftor<
elsif(ladd="
=liftor-1;
endprocessp4;
endlift1_arch;
entitylifteris
--4mhz信号
selout:
outSTD_LOGIC_VECTOR(2downto0);
segout:
outSTD_LOGIC_VECTOR(6downto0)
endlifter;
architecturelift1_archoflifteris
signaldiv,cp,hand,clkin:
signalladd,s:
signaldout:
signalq:
STD_LOGIC_VECTOR(21downto0);
=(notclose)and(notladd
(1));
=(notdelay)and(notladd
(1));
selout<
whens=0else
whens=1else
100"
whens=2else
dout<
=directwhens=0else
run_waitwhens=1else
st_outwhens=2else
0000000"
u:
led1portmap(dout,segout);
q<
=q+1;
cp<
=q(20);
s<
=q(14downto13);
process(cp)
if(cp'
eventandcp='
div<
=notdiv;
))
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