基于FPGA的数字系统设计实验3lcd显示字符OK的程序文档格式.docx
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基于FPGA的数字系统设计实验3lcd显示字符OK的程序文档格式.docx
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assignflash_ce=1;
assignlcd_rw=0;
reg[19:
0]delay_count;
0]num_count;
parameterstate1=6'
b000001;
parameterstate2=6'
b000010;
parameterstate3=6'
b000011;
parameterstate4=6'
b000100;
parameterstate5=6'
b000101;
parameterstate6=6'
b000110;
parameterstate7=6'
b000111;
parameterstate8=6'
b001000;
parameterstate9=6'
b001001;
parameterstate10=6'
b001010;
parameterstate11=6'
b001011;
parameterstate12=6'
b001100;
parameterstate13=6'
b001101;
parameterstate14=6'
b001110;
parameterstate15=6'
b001111;
parameterstate16=6'
b010000;
parameterstate17=6'
b010001;
parameterstate18=6'
b010010;
parameterstate19=6'
b010011;
parameterstate20=6'
b010100;
parameterstate21=6'
b010101;
parameterstate22=6'
b010110;
parameterstate23=6'
b010111;
parameterstate24=6'
b011000;
parameterstate25=6'
b011001;
parameterstate26=6'
b011010;
parameterstate27=6'
b011011;
parameterstate28=6'
b011100;
parameterstate29=6'
b011101;
parameterstate30=6'
b011110;
parameterstate31=6'
b011111;
parameterstate32=6'
b100000;
parameterstate33=6'
b100001;
parameterstate34=6'
b100010;
parameterstate35=6'
b100011;
parameterstate36=6'
b100100;
parameterstate37=6'
b100101;
parameterstate38=6'
b100110;
parameterstate39=6'
b100111;
parameterstate40=6'
b101000;
parameterstate41=6'
b101001;
parameterstate42=6'
b101010;
parameterstate43=6'
b101011;
parameterstate44=6'
b101100;
parameterstate45=6'
b101101;
parameterstate46=6'
b101110;
parameterstate47=6'
b101111;
parameterstate48=6'
b110000;
parameterstate49=6'
b110001;
parameterstate50=6'
b110010;
parameterstate51=6'
b110011;
parameterstate52=6'
b110100;
parameterstate53=6'
b110101;
parameterstate54=6'
b110110;
parameterstate55=6'
b110111;
parameterstate56=6'
b111000;
parameterstate57=6'
b111001;
parameterstate58=6'
b111010;
parameterstate59=6'
b111011;
reg[5:
0]state;
regstate_change;
always@(posedgeclkorposedgereset)
if(reset)
begin
state_change<
=1'
b0;
delay_count<
b1;
end
else
if(delay_count==num_count-1)
=delay_count+1'
always@(posedgestate_changeorposedgereset)
state<
=state1;
num_count<
=20'
d750000;
case(state)
state1:
begin
=state2;
d4;
lcd_rs<
lcd_e<
lcd_d<
=4'
h3;
state2:
=state3;
d12;
state3:
=state4;
d205000;
state4:
=state5;
state5:
=state6;
state6:
=state7;
d5000;
state7:
=state8;
h2;
state8:
=state9;
state9:
=state10;
d4000;
//setfuntionmode
state10:
=state11;
=0;
state11:
=state12;
state12:
=state13;
d80;
state13:
=state14;
h8;
state14:
=state15;
state15:
=state16;
//setentrymode
state16:
=state17;
h0;
state17:
=state18;
state18:
=state19;
state19:
=state20;
h6;
state20:
=state21;
state21:
=state22;
//setdisplayon/off
state22:
=state23;
state23:
=state24;
state24:
=state25;
state25:
=state26;
hc;
state26:
=state27;
state27:
=state28;
//cleardisplay
state28:
=state29;
state29:
=state30;
state30:
=state31;
state31:
=state32;
h1;
state32:
=state33;
state33:
=state34;
d2000;
state34:
=state35;
d82000;
//setDDRAMaddress
state35:
=state36;
state36:
=state37;
state37:
=state38;
state38:
=state39;
state39:
=state40;
state40:
=state41;
//nowstartswritingdatatoDDRAM
state41:
=state42;
h4;
state42:
=state43;
state43:
=state44;
state44:
=state45;
hf;
state45:
=state46;
state46:
=state47;
state47:
=state48;
state48:
=state49;
state49:
=state50;
state50:
=state51;
hb;
state51:
=state52;
state52:
=state53;
state53:
=state54;
state54:
=state55;
state55:
=state56;
state56:
=state57;
state57:
=state58;
state58:
=state59;
state59:
d800;
default:
endcase
endmodule
NET"
clk"
LOC="
C9"
|IOSTANDARD=LVTTL;
flash_ce"
D16"
|IOSTANDARD=LVTTL|DRIVE=2|SLEW=SLOW;
lcd_d<
0>
"
R15"
1>
R16"
2>
P17"
3>
M15"
lcd_e"
M18"
lcd_rs"
L18"
lcd_rw"
L17"
reset"
L13"
|IOSTANDARD=LVTTL|PULLUP;
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