可编程ASIC技术课程设计projectWord格式文档下载.docx
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可编程ASIC技术课程设计projectWord格式文档下载.docx
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elsecnt=cnt+1;
always@(posedgeclk_488ns)
if(cnt==7)clk1=1;
elseclk1=0;
endmodule
复用部分:
moduleSwitch_Mux(out,reset,clk,cnt,d_in0,d_in1,d_in2,d_in3,d_in4,d_in5,d_in6,d_in7,d_in8,d_in9,d_in10,d_in11,d_in12,d_in13,d_in14,d_in15,d_in16,d_in17,d_in18,d_in19,d_in20,d_in21,d_in22,d_in23,d_in24,d_in25,d_in26,d_in27,d_in28,d_in29,d_in30,d_in31);
output[7:
0]out;
inputreset,clk;
input[4:
input[7:
0]d_in0,d_in1,d_in2,d_in3,d_in4,d_in5,d_in6,d_in7,d_in8,d_in9,d_in10,d_in11,d_in12,d_in13,d_in14,d_in15,d_in16,d_in17,d_in18,d_in19,d_in20,d_in21,d_in22,d_in23,d_in24,d_in25,d_in26,d_in27,d_in28,d_in29,d_in30,d_in31;
reg[7:
0]d_buf;
assignout=d_buf;
always@(posedgeclkornegedgereset)
if(!
reset)d_buf=0;
else
case(cnt)
5'
b0_0000:
d_buf=d_in0;
b0_0001:
d_buf=d_in1;
b0_0010:
d_buf=d_in2;
b0_0011:
d_buf=d_in3;
b0_0100:
d_buf=d_in4;
b0_0101:
d_buf=d_in5;
b0_0110:
d_buf=d_in6;
b0_0111:
d_buf=d_in7;
b0_1000:
d_buf=d_in8;
b0_1001:
d_buf=d_in9;
b0_1010:
d_buf=d_in10;
b0_1011:
d_buf=d_in11;
b0_1100:
d_buf=d_in12;
b0_1101:
d_buf=d_in13;
b0_1110:
d_buf=d_in14;
b0_1111:
d_buf=d_in15;
b1_0000:
d_buf=d_in16;
b1_0001:
d_buf=d_in17;
b1_0010:
d_buf=d_in18;
b1_0011:
d_buf=d_in19;
b1_0100:
d_buf=d_in20;
b1_0101:
d_buf=d_in21;
b1_0110:
d_buf=d_in22;
b1_0111:
d_buf=d_in23;
b1_1000:
d_buf=d_in24;
b1_1001:
d_buf=d_in25;
b1_1010:
d_buf=d_in26;
b1_1011:
d_buf=d_in27;
b1_1100:
d_buf=d_in28;
b1_1101:
d_buf=d_in29;
b1_1110:
d_buf=d_in30;
b1_1111:
d_buf=d_in31;
default:
d_buf=8'
b0_0000;
endcase
解复用部分:
moduleSwitch_Demux(reset,clk,clk1,flag,cnt,data_in,d_out0,d_out1,d_out2,d_out3,d_out4,d_out5,d_out6,d_out7,d_out8,d_out9,d_out10,d_out11,d_out12,d_out13,d_out14,d_out15,d_out16,d_out17,d_out18,d_out19,d_out20,d_out21,d_out22,d_out23,d_out24,d_out25,d_out26,d_out27,d_out28,d_out29,d_out30,d_out31);
inputreset,clk,clk1,flag;
0]data_in;
input[4:
0]cnt;
output[7:
0]d_out0,d_out1,d_out2,d_out3,d_out4,d_out5,d_out6,d_out7,d_out8,d_out9,d_out10,d_out11,d_out12,d_out13,d_out14,d_out15,d_out16,d_out17,d_out18,d_out19,d_out20,d_out21,d_out22,d_out23,d_out24,d_out25,d_out26,d_out27,d_out28,d_out29,d_out30,d_out31;
reg[7:
0]d_out0,d_out1,d_out2,d_out3,d_out4,d_out5,d_out6,d_out7,d_out8,d_out9,d_out10,d_out11,d_out12,d_out13,d_out14,d_out15,d_out16,d_out17,d_out18,d_out19,d_out20,d_out21,d_out22,d_out23,d_out24,d_out25,d_out26,d_out27,d_out28,d_out29,d_out30,d_out31;
0]dabuf;
always@(negedgeclkornegedgereset)
dabuf=0;
end
elsedabuf=data_in;
alwaysbegin:
ab
@(negedgeclk)
if(!
clk1)disableab;
else
@(negedgeclk)
if(!
flag)disableab;
else
@(negedgeclk)
case(cnt)
d_out0=debuf;
d_out1=debuf;
d_out2=debuf;
d_out3=debuf;
d_out4=debuf;
d_out5=debuf;
d_out6=debuf;
d_out7=debuf;
d_out8=debuf;
d_out9=debuf;
d_out10=debuf;
d_out11=debuf;
d_out12=debuf;
d_out13=debuf;
d_out14=debuf;
d_out15=debuf;
d_out16=debuf;
d_out17=debuf;
d_out18=debuf;
d_out19=debuf;
d_out20=debuf;
d_out21=debuf;
d_out22=debuf;
d_out23=debuf;
d_out24=debuf;
d_out25=debuf;
d_out26=debuf;
d_out27=debuf;
d_out28=debuf;
d_out29=debuf;
d_out30=debuf;
d_out31=debuf;
endcase
end
串口到并口部分:
moduleserial_2_parallel(paral_data,cnt,sda,reset,clk,clk1,flag);
0]paral_data;
outputflag;
inputsda,reset,clk,clk1;
input[2:
regflag;
0]debuf;
always@(negedgeclk1)
paral_data=debuf;
if(!
reset)begindebuf=0;
flag=0;
else
begin
case(cnt)
3'
b001:
begindebuf[7]=sda;
b010:
debuf[6]=sda;
b011:
debuf[5]=sda;
b100:
debuf[4]=sda;
b101:
debuf[3]=sda;
b110:
debuf[2]=sda;
b111:
debuf[1]=sda;
b000:
begindebuf[0]=sda;
flag=1;
endcase
end
并口到串口部分:
moduleparallel_2_serial(seria_out,clk,reset,cnt,data_in);
outputseria_out;
inputclk,reset;
0]data_in;
input[2:
reg[7:
0]databuf;
regseria_buf;
assignseria_out=seria_buf;
always@(data_in)
databuf=data_in;
always@(posedgeclkornegedgereset)
reset)seria_buf=0;
begin
seria_buf=databuf[7];
seria_buf=databuf[6];
seria_buf=databuf[5];
seria_buf=databuf[4];
seria_buf=databuf[3];
seria_buf=databuf[2];
seria_buf=databuf[1];
seria_buf=databuf[0];
default:
seria_buf=0;
endcase
end
测试部分:
`timescale1ns/1ns
moduletest;
regclk,reset,frame_synch;
reg[7:
wire[7:
0]d_out0,d_out1,d_out2,d_out3,d_out4,d_out5,d_out6,d_out7,d_out8,d_out9,d_out10,d_out11,d_out12,d_out13,d_out14,d_out15,d_out16,d_out17,d_out18,d_out19,d_out20,d_out21,d_out22,d_out23,d_out24,d_out25,d_out26,d_out27,d_out28,d_out29,d_out30,d_out31;
0]mux_out;
wire[4:
0]cnt1;
wire[2:
0]cnt2;
wiresda;
0]pda;
wireclk1;
wireflag;
reg[2:
0]k;
parameterCLK_CYCLE=488;
always#(CLK_CYCLE/2)clk=~clk;
initial
begin
clk=1;
reset=1;
frame_synch=0;
d_in0=7;
d_in1=6;
d_in2=5;
d_in3=4;
d_in4=3;
d_in5=2;
d_in6=1;
d_in7=2;
d_in8=3;
d_in9=4;
d_in10=5;
d_in11=6;
d_in12=7;
d_in13=8;
d_in14=9;
d_in15=10;
d_in16=11;
d_in17=12;
d_in18=13;
d_in19=14;
d_in20=15;
d_in21=16;
d_in22=17;
d_in23=18;
d_in24=19;
d_in25=20;
d_in26=21;
d_in27=22;
d_in28=23;
d_in29=24;
d_in30=25;
d_in31=26;
#(CLK_CYCLE/2)reset=0;
#(5*CLK_CYCLE/4)reset=1;
for(k=0;
k=5;
k=k+1)
begin
#(256*CLK_CYCLE+CLK_CYCLE/4)frame_synch=1;
#(CLK_CYCLE/4)frame_synch=0;
d_in0=1+k;
d_in1=2+k;
d_in2=3+k;
d_in3=4+k;
d_in4=5+k;
d_in5=6+k;
d_in6=7+k;
d_in7=8+k;
d_in8=9+k;
d_in9=10+k;
d_in10=11+k;
d_in11=12+k;
d_in12=13+k;
d_in13=14+k;
d_in14=15+k;
d_in15=16+k;
d_in16=17+k;
d_in17=18+k;
d_in18=19+k;
d_in19=20+k;
d_in20=21+k;
d_in21=22+k;
d_in22=23+k;
d_in23=24+k;
d_in24=25+k;
d_in25=26+k;
d_in26=27+k;
d_in27=28+k;
d_in28=29+k;
d_in29=30+k;
d_in30=31+k;
d_in31=32+k;
end
#(260*CLK_CYCLE)$stop;
end
Switch_Muxm0(mux_out,reset,clk,cnt1,d_in0,d_in1,d_in2,d_in3,d_in4,d_in5,d_in6,d_in7,d_in8,d_in9,d_in10,d_in11,d_in12,d_in13,d_in14,d_in15,d_in16,d_in17,d_in18,d_in19,d_in20,d_in21,d_in22,d_in23,d_in24,d_in25,d_in26,d_in27,d_in28,d_in29,d_in30,d_in31);
parallel_2_serialm1(sda,clk,reset,cnt2,mux_out);
serial_2_parallelm2(pda,cnt2,sda,reset,clk,clk1,flag);
Switch_Demuxm3(reset,clk,clk1,flag,cnt1,pda,d_out0,d_out1,d_out2,d_out3,d_out4,d_out5,d_out6,d_out7,d_out8,d_out9,d_out10,d_out11,d_out
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