Verilog程序.docx
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Verilog程序.docx
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Verilog程序
moduleantitwitter(clock,keyin,keyout);
inputclock,keyin;
outputkeyout;
reg[3:
0]count;
regkeyout;
always@(posedgeclock)
begin
if(keyin==1)
begin
count<=count+4'h1;
if(count<=8)keyout<=1'b0;
else
begin
keyout<=keyin;
count<=4'h9;
end
end
else
begin
count<=4'h0;
keyout<=1'b0;
end
end
endmodule
modulediscode38(g1,g2a,g2b,a,b,c,y);
inputg1,g2a,g2b,a,b,c;
output[7:
0]y;
reg[7:
0]y;
always@(g1org2aorg2boraorborc)//当输入信号有变化时,执行块语句
begin
if((g1==1)&&(g2a==0)&&(g2b==0))//门控信号满足条件时,输出有效
begin
case({c,b,a})
3'b000:
y<=8'b11111110;
3'b001:
y<=8'b11111101;
3'b010:
y<=8'b11111011;
3'b011:
y<=8'b11110111;
3'b100:
y<=8'b11101111;
3'b101:
y<=8'b11011111;
3'b110:
y<=8'b10111111;
3'b111:
y<=8'b01111111;
default:
y<=8'b11111111;
endcase
end
elsey<=8'b11111111;
end
endmodule
modulefredevider2(clockin,clockout);
inputclockin;
outputclockout;
regclockout;
always@(posedgeclockin)
begin
clockout<=~clockout;
end
endmodule
modulefredevider3(clockin,clockout);
inputclockin;
outputclockout;
regtemp1,temp2;
reg[1:
0]count;
always@(posedgeclockin)
begin
if(count==2)
begin
count<=0;
temp1<=~temp1;
end
else
count<=count+1;
end
always@(negedgeclockin)
begin
if(count==1)
temp2<=~temp2;
end
assignclockout=temp1^temp2;
endmodule
modulefredevider4(clockin,clockout);
inputclockin;
outputclockout;
reg[1:
0]count;
regclockout;
parameterN=0;
always@(posedgeclockin)
begin
if(count==N)//每计到2个上升沿(从0开始)时,输出信号翻转一次
begin
count<=2'b00;
clockout<=~clockout;
end
count<=count+2'b01;
end
endmodule
modulefredevider6(clockin,clockout);
inputclockin;
outputclockout;
reg[2:
0]count;
regclockout;
parameterN=2;
always@(posedgeclockin)
begin
if(count==N)//每计到2个上升沿(从0开始)时,输出信号翻转一次
begin
count<=3'b000;
clockout<=~clockout;
end
else
count<=count+3'b001;
end
endmodule
moduleseg_7(code,discode);
input[3:
0]code;
output[6:
0]discode;
reg[6:
0]discode;
always@(code)//如果输入发生变化,则执行下面块语句
begin
case(code)
4'b0000:
discode<=7'b1111110;
4'b0001:
discode<=7'b0110000;
4'b0010:
discode<=7'b1101101;
4'b0011:
discode<=7'b1111001;
4'b0100:
discode<=7'b0110011;
4'b0101:
discode<=7'b1011011;
4'b0110:
discode<=7'b0011111;
4'b0111:
discode<=7'b1110000;
4'b1000:
discode<=7'b1111111;
4'b1001:
discode<=7'b1110011;
defaultdiscode<=7'b0000000;
endcase
end
endmodule
moduleseg_flash(clock,code,discode);
inputclock;
input[3:
0]code;
output[6:
0]discode;
reg[6:
0]discode;
reg[7:
0]count;
always@(posedgeclock)
begin
if(count==128)
count<=0;
else
count<=count+1;
end
always@(posedgeclock)
begin
if(count<=64)//计数值小于64,显示输出
begin
case(code)
4'b0000:
discode<=7'b1111110;
4'b0001:
discode<=7'b0110000;
4'b0010:
discode<=7'b1101101;
4'b0011:
discode<=7'b1111001;
4'b0100:
discode<=7'b0110011;
4'b0101:
discode<=7'b1011011;
4'b0110:
discode<=7'b0011111;
4'b0111:
discode<=7'b1110000;
4'b1000:
discode<=7'b1111111;
4'b1001:
discode<=7'b1110011;
defaultdiscode<=7'b0000000;
endcase
end
elsediscode<=7'b0000000;//计数值大于64则不显示
end
endmodule
modulekeyboard(key4in,key4out,codeout,clock,reset,count);
input[3:
0]key4in;
inputclock,reset;
output[3:
0]key4out,codeout,count;
reg[3:
0]key4out,codeout;
reg[7:
0]count;
reg[5:
0]state;
parameter
firststate=6'b000001,
waitst=6'b000010,
scan1=6'b000100,
scan2=6'b001000,
scan3=6'b010000,
scan4=6'b100000;
always@(posedgeclock)
begin
if(reset)
begin
state<=firststate;
count<=8'b00000000;
codeout<=4'bz;
end
else
begin
case(state)
firststate:
begin
key4out<=4'b1111;
if(|(key4in))
state<=waitst;
else
state<=firststate;
end
waitst:
begin
if(count<=19)
begin
state<=waitst;
count<=count+1'b1;
end
else
begin
count<=8'b00000000;
state<=scan1;
key4out<=4'b0001;
end
end
scan1:
begin
if(|(key4in))
begin
case(key4in)
4'b0001:
codeout<=4'h0;
4'b0010:
codeout<=4'h1;
4'b0100:
codeout<=4'h2;
4'b1000:
codeout<=4'h3;
default:
codeout<=4'hz;
endcase
state<=firststate;
end
else
begin
state<=scan2;
key4out=4'b0010;
end
end
scan2:
begin
if(|(key4in))
begin
case(key4in)
4'b0001:
codeout<=4'h4;
4'b0010:
codeout<=4'h5;
4'b0100:
codeout<=4'h6;
4'b1000:
codeout<=4'h7;
default:
codeout<=4'hz;
endcase
state<=firststate;
end
else
begin
state<=scan3;
key4out=4'b0100;
end
end
scan3:
begin
if(|(key4in))
begin
case(key4in)
4'b0001:
codeout<=4'h8;
4'b0010:
codeout<=4'h9;
4'b0100:
codeout<=4'ha;
4'b1000:
codeout<=4'hb;
default:
codeout<=4'hz;
endcase
state<=firststate;
end
else
begin
state<=scan4;
key4out=4'b1000;
end
end
scan4:
begin
if(|(key4in))
begin
case(key4in)
4'b0001:
codeout<=4'hc;
4'b0010:
codeout<=4'hd;
4'b0100:
codeout<=4'he;
4'b1000:
codeout<=4'hf;
default:
codeout<=4'bz;
endcase
state<=firststate;
end
else
begin
state<=firststate;
key4out=4'b0010;
end
end
endcase
end
end
endmodule
modulefrediv2(clockin,clkout);
inputclockin;
outputclkout;
regclkout;
always@(posedgeclockin)
clkout<=!
clkout;
endmodule
modulefrediv10(clockin,clkout);
inputclockin;
outputclkout;
regclkout;
reg[3:
0]counter;
always@(posedgeclockin)
begin
if(counter==4)
begin
clkout<=!
clkout;
counter<=0;
end
elsecounter<=counter+1;
end
endmodule
modulemmcount(clockmmin,reset,mmouta,mmoutb,clockmout,alarm);
inputclockmmin,reset;
outputclockmout,alarm;
output[3:
0]mmouta,mmoutb;
regclockmout,alarm;
reg[3:
0]mmouta,mmoutb;
reg[7:
0]countnum;
always@(posedgeclockmmin)
begin
if(reset)
begin
countnum<=0;
mmouta<=0;
mmoutb<=0;
end
else
begin
if(countnum==29)
clockmout<=!
clockmout;
if(countnum==59)
begin
clockmout<=!
clockmout;
alarm<=1;
countnum<=0;
mmouta<=0;
mmoutb<=0;
end
else
begin
countnum<=countnum+1;
if(mmouta==9)
begin
mmouta<=0;
mmoutb<=mmoutb+1;
end
else
begin
mmouta<=mmouta+1;
end
end
end
end
endmodule
modulemscount(clockmsin,reset,msouta,msoutb,clocksout);
inputclockmsin,reset;
outputclocksout;
output[3:
0]msouta,msoutb;
regclocksout;
reg[3:
0]msouta,msoutb;
reg[7:
0]countnum;
always@(posedgeclockmsin)
begin
if(reset)
begin
countnum<=0;
msouta<=0;
msoutb<=0;
end
else
begin
if(countnum==49)
clocksout<=!
clocksout;
if(countnum==99)
begin
clocksout<=!
clocksout;
countnum<=0;
msouta<=0;
msoutb<=0;
end
else
begin
countnum<=countnum+1;
if(msouta==9)
begin
msouta<=0;
msoutb<=msoutb+1;
end
else
begin
msouta<=msouta+1;
end
end
end
end
endmodule
modulestartcontroller(start,stop,clock,dataout);
inputstart,stop,clock;
outputdataout;
regdataout1;
wiredataout;
always@(posedgestartorposedgestop)
begin
if(stop)dataout1<=0;
elsedataout1<=1;
end
assigndataout=dataout1&clock;
endmodule
modulesuosun(start,clear,clock,dataout);
inputstart,clear,clock;
outputdataout;
regdataout1;
wiredataout;
always@(posedgestartorposedgeclear)
begin
if(clear)dataout1<=0;
elsedataout1<=1;
end
assigndataout=dataout1&clock;
endmodule
moduledisplay1(clock,code,discode);
inputclock;
input[3:
0]code;
output[6:
0]discode;
reg[6:
0]discode;
always@(posedgeclock)
begin
case(code)
4'b0000:
discode<=7'b1111110;
4'b0001:
discode<=7'b0110000;
4'b0010:
discode<=7'b1101101;
4'b0011:
discode<=7'b1111001;
4'b0100:
discode<=7'b0110011;
4'b0101:
discode<=7'b1011011;
4'b0110:
discode<=7'b0011111;
4'b0111:
discode<=7'b1110000;
4'b1000:
discode<=7'b1111111;
4'b1001:
discode<=7'b1110011;
defaultdiscode<=7'b0000000;
endcase
end
endmodule
分频10
modulefenpin10(clockin,clkout);
inputclockin;
outputclkout;
regclkout;
reg[3:
0]counter;
always@(posedgeclockin)
begin
if(counter==4)
begin
clkout<=!
clkout;
counter<=0;
end
elsecounter<=counter+1;
end
endmodule
分频100
modulefenpin100(clockin,clkout);
inputclockin;
outputclkout;
regclkout;
reg[7:
0]counter;
always@(posedgeclockin)
begin
if(counter==49)
begin
clkout<=!
clkout;
counter<=0;
end
elsecounter<=counter+1;
end
endmodule
[hcounter]:
modulehcounter(clock,dcodea,dcodeb,reset);
inputclock,reset;
output[3:
0]dcodea,dcodeb;
regclkout;
reg[3:
0]dcodea,dcodeb;
reg[7:
0]countnum;
always@(posedgeclock)
begin
if(reset)
begin
countnum<=0;
dcodea<=0;
dcodeb<=0;
end
else
begin
if(countnum==11)
begin
countnum<=0;
dcodea<=0;
dcodeb<=0;
end
else
begin
countnum<=countnum+1;
if(dcodea==9)
begin
dcodea<=0;
dcodeb<=dcodeb+1;
end
else
begin
dcodea<=dcodea+1;
end
end
end
end
endmodule
[ledlat]:
moduleledlat(clock,clkin,codein,codeout,selout,clkout);
inputclock,clkin;
input[7:
0]codein;
output[7:
0]codeout,selout;
outputclkout;
reg[7:
0]codeout,selout;
regclkout;
reg[7:
0]mymemory[7:
0];
reg[4:
0]count1,count2;
always@
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