数字电路与逻辑设计11.ppt
- 文档编号:16157969
- 上传时间:2023-07-11
- 格式:PPT
- 页数:41
- 大小:2.27MB
数字电路与逻辑设计11.ppt
《数字电路与逻辑设计11.ppt》由会员分享,可在线阅读,更多相关《数字电路与逻辑设计11.ppt(41页珍藏版)》请在冰点文库上搜索。
,DigitalFundamentalsTenthEditionFloyd,Chapter11,Summary,ProgrammableLogic,SPLD:
(SimplePLDs)aretheearliesttypeofarraylogicusedforfixedfunctionsandsmallercircuitswithalimitednumberofgates.(ThePALandGALarebothSPLDs).CPLD:
(ComplexPLDs)aremultipleSPLDsarraysandinter-connectionarraysonasinglechip.FPLD:
(FieldProgrammableGateArray)areamoreflexiblearrangementthanCPLDs,withmuchlargercapacity.,ProgrammableLogicDevices(PLDs)areICswithalargenumberofgatesandflipflopsthatcanbeconfiguredwithbasicsoftwaretoperformaspecificlogicfunctionorperformthelogicforacomplexcircuit.MajortypesofPLDsare:
Summary,ProgrammableLogic,AdvantagestoPLDsinclude,ReducedcomplexityofcircuitboardsLowerpowerrequirementsLessboardspaceSimplertestingproceduresHigherreliabilityDesignflexibility,Summary,PALsandGALs,PALshaveaonetimeprogrammable(OTP)array,inwhichfusesarepermanentlyblown,creatingtheproducttermsinanANDarray.,AllPLDscontainarrays.TwoimportantSPLDsarePALs(ProgrammableArrayLogic)andGALs(GenericArrayLogic).AtypicalarrayconsistsofamatrixofconductorsconnectedinrowsandcolumnstoANDgates.,SimplifiedAND-ORarray,X,AABB,Summary,X,AABB,Whatfunctionisrepresentedbythearray?
Example,Solution,ThefunctionrepresentsanXORgate.,X=AB+AB,PALsareprogrammedwithaspecializedprogrammerthatblowsselectedinternalfuselinks.Afterblowingthefuses,thearrayrepresentstheBooleanlogicexpressionforthedesiredcircuit.,PALsandGALs,Summary,TheGAL(GenericArrayLogic)issimilartoaPALbutcanbereprogrammed.Forthisreason,theyareusefulfornewproductdevelopment(prototyping)andfortrainingpurposes.,AABB,X,GALsweredevelopedbyLatticeSemiconductor.Theyarehighspeed,extremelyfastdevicesandcaninterfacewithboth3.3Vor5Vlogicsignals.,PALsandGALs,Summary,PALsandGALscanberepresentedwithasimplifieddiagram.Asinglelinecanrepresentmultiplegateinputs.ThelogicshownisfortheXORgate,givenpreviously.,Inputbuffer,AABB,SinglelinewithslashindicatingmultipleANDgateinputs,Fuseblown,Fuseintact,AB,AB,AB+AB,PALsandGALs,Summary,PALsandGALshavelargearraylogicandincludeoutputlogicthatvariesincomplexity.TheoutputlogicisconnectedtoeachORgateandtogetherisreferredtoasamacrocell.TwotypesofPAL/GALmacrocellsareshown.Fortheseparticularmacrocells,theI/Opinscanserveasaninputoranoutput.,Tristatecontrol,FromANDarray,FromANDarray,I/O,I/O,Programmablefuselinktocontroloutputpolarity,ToANDarray,ToANDarray,PALsandGALs,Summary,ThePAL16V8isatypicalSPLD.Thereare16pinsthatcanbeusedasinputsand8pinsthatcanbeusedasoutputs.I/Opinsarecountedasbothinputsandoutputs.,I1,I2,I3,I4,I5,I6,I7,I8,I9,I/O10,O1,I/O1,I/O2,I/O3,I/O4,I/O5,I/O6,O2,ProgrammableANDarray,PLCCPackage,PALsandGALs,Summary,CPLDs,Acomplexprogrammablelogicdevice(CPLD)hasmultiplelogicarrayblocks(LABs)thatareactuallySPLDsonasingleIC.LABsareconnectedviaaprogrammableinterconnectarray(PIA).VariousCPLDshavedifferentstructuresfortheseelements.,ThePIAistheinterconnectionbetweentheLABs.LogicisfittedtotheCPLDandroutingisdeterminedbyahigh-levelprogramminglanguagecalledahardwaredescriptionlanguage(HDL).,Summary,CPLDs,ThearchitectureofaCPLDisthewayinwhichtheinternalelementsareconfigured.AportionoftheAlteraMAX7000seriesisshown.ThisstructureistypicalforCPLDsalthoughdensities,size,speed,andinternalfactors(macrocells,etc)willvarybetweenmanufacturers.,I/Opins,I/Opins,General-purposeinputs,Summary,CPLDs,MacrocellsintheAlteraMAX7000seriescangenerateuptofiveproductterms.Forexpressionsrequiringmoreterms,theoutputcanbeexpandedasdescribedinthetext.,Summary,Macrocells,Inadditiontocombinationlogic,somemacrocellshaveregisteredoutputsavailable(usingprogrammableflip-flops).ThisallowstheCPLDtoperformsequentiallogic.,Summary,FPGAs,Afieldprogrammablegatearray(FPGA)usesadifferentarchitecturethanaCPLD.Theconfigurablelogicblock(CLB)isthebasicelementwhichisreplicatedmanytimes.,CLBsarearrangedinarowandcolumnstructure.WithintheCLBsarelogicmodulesjoinedbylocalinterconnects.Generally,thelogicmodulesarecomposedofalook-uptable(LUT),aflip-flop,andaMUXthatcanbeusedtobypasstheflip-flopforstrictlycombinationallogic.,Summary,FPGAs,Logicmodulescanbeconfiguredforcombinationallogic,registeredlogic,oracombinationofboth.Theglobalinterconnectsdistributesignals(includingtheclock)tovariousCLBs.,FPGAsmayalsohaveahardcoreportionoflogicthatisputinbythemanufacturerandcannotbereprogrammedbytheuser.TheseFPGAsareusefulincommonlyusedfunctionssuchasI/Ointerfaces.,Summary,ProgrammableLogicSoftware,Allmanufacturersofprogrammablelogicprovidesoftwaretosupporttheirproducts.Theprocessisillustratedintheflowchart.,Thefirststepistoenterthelogicdesignintoacomputer.Itisdoneinoneoftwoways:
1)Schematicentry2)Hardwaredescriptionlanguage(HDL).,Summary,ProgrammableLogicSoftware,Inschematicentry,thedesignisdrawnonacomputerscreenbyplacingcomponentsandconnectingthenwithsimulatedwires.YoudonotneedtoknowthedetailsofanHDL.Afterdrawingtheschematic,itcanbereducedtoasingleblocksymbol:
Summary,ProgrammableLogicSoftware,Intextentry,thedesignisenteredviaahardwaredescriptionlanguagesuchasVHDLorVerilog.,VHDLhastwokeyparts:
theentityandthearchitecture.Theentitysectiondescribestheinputs,outputs,andvariables.ThearchitecturesectiondescribestherelationshipsbetweenvariablesusingBooleanequations.TheVHDLequationcanbeunderstood,evenifyoudonotknowVHDL.,Forexample,theVHDLexpressionforLED1iswrittenas,LED1=(DXORC)XORB)XORA;,Summary,ProgrammableLogicSoftware,ThecompleteVHDLprogramforthiscomponentisshownonthefollowingslide.,VHDLallowsyoutodescribecomponentsinoneprogramandthenusetheminanotherprogram.,Forexample,anactive-LOWS-Rlatchcanbedrawnas,Summary,ProgrammableLogicSoftware,entityS_RLatchisport(A,B:
inbit;Q,QNot:
inoutbit);endentityS_RLatch;architectureBehaviorofS_RLatchisbeginQ=notAornotQNot;QNot=notBornotQ;endarchitectureBehavior;,Entitysection,Architecturesection,Summary,FunctionalSimulation,AfterenteringthecircuitintoanHDL(suchasVHDL),thecircuitistestedinafunctionalsimulation.ThefunctionalsimulationispartoftheHDL.Youcantestthecircuitwithwaveformstoverifytheoperation.,Thefollowingshowsthefunctionaltestofacounterusingawaveformeditor:
Example,Summary,Synthesis,Afterthesimulation,thecomputerprogramoptimizesthelogicbyeliminatingredundanttermsandgeneratinganetlist,(aconnectionlist)thatisacompletedescriptionofthecircuit.,Netlist,Summary,Implementation,Thecomputernext“maps”thedesignfromthenetlisttofitittoatargetdevice.Dataforallpotentialtargetdevicesareinasoftwarelibrary.ThecomputermustaccountfortheI/Opinsandfitthelogictothetargetdevice.,Summary,TimingSimulation,Afterimplementation,atimingsimulationisdonethattakesintoaccountthespecificdelaysinthetargetdeviceandverifiesthattherenoproblemswiththetiming.Asinthecaseofthefunctionalsimulation,thewaveformeditorcanbeusedtoreviewfinaltiming.,Ifaproblemisrevealed,itisnottoolatetocorrectitbeforedownloadingthefile.,Summary,DeviceProgramming,Thefinalstepistosendtheprogrammingfilefromthecomputertothetargetdeviceandtesttheimplementation.,APLDT-2prototypingboardthathasanAlteraPLDasthetargetdeviceisshown.Connectionsareaddedtotheboardfromapulsegeneratorandoscilloscopetotesttheactualcircuitinalaboratoryenvironment.Theprototypingboardhasbuilt-inpowersupplies,interfacing,I/O,andmore.,Summary,Testing,ThetrafficlightsystemapplicationwasdescribedinseveralSystemApplicationActivitiesinthetext.ThephotographisthetrafficlightlogicdownloadedtoaPLDT-2boardandoperatingasimulatedtrafficlight.Aninterfaceisaddedtoallowforthevoltageandcurrentrequirementsofthebulbs.,Interfaceboard,PLDT-2board,Summary,BoundaryScanLogic,Boundaryscanthatisdesignedbythemanufacturerofprogrammabledevicestoprovideameansoftestingandprogrammingthedevicewithoutrequiringphysicalaccesstotheinternallogic.Programmabledevicesthatarecompliantwithacertainstandardhaveinternalregisterstoallowtestingofinternalinterconnectionsandlogic.Testdataissuppliedandverified.Whenthecircuitisoperating,theboundaryscanlogicis“invisible”.,Thefollowingslideshowsaboundaryscanlogicdiagram,Summary,BoundaryScanLogic,SelectedKeyTerms,PALGALMacrocellCPLD,Atypeofone-timeprogrammableSPLDthatconsistsofaprogrammablearrayofANDgatesthatconnectstoafixedarrayofORgates.,AreprogrammabletypeofSPLDthatthatissimilartoaPALexceptitusesareprogrammableprocesstechnology,suchasEEPROMinsteadoffuses.,PartofaPAL,GAL,orCPLDthatgenerallyconsistsofoneORgateandsomeassociatedoutputlogic.,AcomplexreprogrammablelogicdevicethatconsistsbasicallyofmultipleSPLDarrayswithprogrammableinterconnections.,SelectedKeyTerms,FPGADesignflowSchematicentryTextentryBoundaryscan,Fieldprogrammablegatearray;aprogrammablelogicdevicethatusestheLUTasthebasiclogicelementandgenerallyemployseithertheantifuseorSRAM-basedprocesstechnology,Theprocessorsequencecarriedouttoprogramatargetdevice.,Amethodofplacingalogicdesignintosoftwareusingschematicsymbols.,Amethodofplacingalogicdesignintosoftwareusing
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 数字电路 逻辑设计 11