硬件配置字.docx
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硬件配置字.docx
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硬件配置字
1.
ThesystemPLLinputsestablishtheclockratiobetweentheSYSCLKinputandtheplatformclockusedbytheP2020.Theplatformclock,calledthecorecomplexbus(CCB)clock,drivestheL2cache,theDDRSDRAMdatarate.
2.
TheDDRPLLinputs,establishtheclockratiobetweentheDDRCLKinputandtheDDRcontrollerclock.TheDDRcontrollerclockdrivestheDDRdatarate,whichistwicetherateatwhichcommandsareissuedontheDDRinterfacewhenDDRclockselectiszero.ThisDDRcontrollerclockdomainisasynchronoustotheplatformclockorCCBclockdomainandissourcedfromaseparatePLLthantherestoftheplatform,unlesstheDDRPLLencodingforsynchronousmodeoperationisselected.
Whensynchronousmodeisselected,theDDRcontrollerisdrivenbytheCCBclock,whichbecomestheDDRdatarate.
3.
e500coreclockPLL
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TheP2020definesthedefaultbootROMaddressrangetobe8Mbytesataddress0x0_FF80_0000to0x0_FFFF_FFFF.However,whichperipheralinterfacehandlesthesebootROMaccessescanbeselectedatpoweron.
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Thehost/agentresetconfigurationinputs,configuretheP2020toactasahostorasanagentofamasteronanotherinterface.
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TheP2020canbeconfiguredwithdifferentI/Oportsactive.
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TheeTSECwidthinput,selectsstandardversusreducedwidthforthree-speedEthernetcontrollerinterfaces1and2operatinginparallelmode.
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TheRapidIOdeviceIDinputs,specifythethreelower-orderbitsofthedeviceIDof
theP2020asusedbyRapidIOhosts.Notethatthe5high-orderRapidIOdeviceIDbitscannotbesetthroughthePORconfigurationinputs.TheymaybeinitializedbythebootsequencerorbytheprocessorfrombootROMorbytheRapidIOdiscoveryprocess.
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TheRapidIOcommontransportspecificationdefinestwosystemsizes.Thelargesizeuses16-bitsourceanddestinationIDsallowingfor65,536devices,whilethesmallsizeuses8-bitsourceanddestinationIDs,supporting256devices.
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TheeLBCaddress/databusinputs,ThisregisterisintendedtofacilitatePORconfigurationofusersystems.AvalueplacedonLAD[0:
31]duringPORiscapturedandstored(readonly)intheGPPORCR.Softwarecanthenusethisvaluetoinformtheoperatingsystemaboutinitialsystemconfiguration.Typicalinterpretationsincludecircuitboardtype,boardIDnumber,oralistofavailableperipherals.
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TheSYSCLKspeedconfigurationinputconfiguresinternallogicforproperoperationwiththeSYSCLKclockfrequenciesinuse.ThedefaultsettingisappropriateforSYSCLKoperatingatorabove66MHz.Forlowspeedoperation(SYSCLKbelow66MHz)thisPORconfigurationinputshouldbelowduringHRESET.Ifthisconfigurationisnotsetproperly,behaviorofthesystemmaybeunreliable.
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Theplatformspeedconfigurationinput,configuresinternallogicforproperoperationwiththeplatformclockfrequenciesinuse.Thedefaultsettingisappropriateforplatformoperatingatorabove333MHz.Forlowspeedoperation(platformbelow333MHz)thisPORconfigurationinputshouldbelowduringHRESET.
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