电子eda实验考试题目.docx
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电子eda实验考试题目.docx
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电子eda实验考试题目
设计实验与考核
1、设计一个带计数使能、同步复位、带进位输出的增1六位二进制计数器,计数结果由共阴极七段数码管显示。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port(clk,clk1,en,clr:
instd_logic;
ledout:
outstd_logic_vector(6downto0);
scanout,co:
outstd_logic);
endcounter;
architectureaofcounteris
signalcnt:
std_logic_vector(7downto0);
signalled:
std_logic_vector(6downto0);
signalscan:
std_logic;
signalhex:
std_logic_vector(3downto0);
begin
process(clk)
begin
if(clk'eventandclk='1')then
ifen='1'then
ifclr='1'then
cnt<=(others=>'0');
else
ifcnt="00111111"then
cnt<="00000000";
co<='1';
else
cnt<=cnt+'1';
co<='0';
endif;
endif;
endif;
endif;
endprocess;
process(clk1)
begin
ifclk1'eventandclk1='1'then
scan<=notscan;
endif;
endprocess;
ledout<=notled;
scanout<=scan;
hex<=cnt(7downto4)whenscan='1'elsecnt(3downto0);
withhexselect
led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"0001000"when"1010",
"0000011"when"1011",
"1000110"when"1100",
"0100001"when"1101",
"0000110"when"1110",
"0001110"when"1111",
"1000000"whenothers;
enda;
2、设计一个带计数使能、异步复位、带进位输出的增1二十进制计数器,计数结果由共阴极七段数码管显示
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port(clk,clk1,en,clr:
instd_logic;
co,scanout:
outstd_logic;
ledout:
outstd_logic_vector(6downto0));
endcounter;
architecturertlofcounteris
signalcnt:
std_logic_vector(7downto0);
signalled:
std_logic_vector(6downto0);
signalscan:
std_logic;
signalhex:
std_logic_vector(3downto0);
begin
process(clk,clr)
begin
ifclr='1'then
cnt<=(others=>'0');
elsifclk'eventandclk='1'then
ifen='1'then
ifcnt="00001001"then
cnt<="00010000";
co<='0';
elsifcnt="00011001"then--注意此处,前面跳过了A到F的计数,所以计数到11001
cnt<="00000000";
co<='1';
else
cnt<=cnt+'1';
co<='0';
endif;
endif;
endif;
endprocess;
process(clk1)
begin
ifclk1'eventandclk1='1'then
scan<=notscan;
endif;
endprocess;
ledout<=notled;
scanout<=scan;
hex<=cnt(7downto4)whenscan='1'elsecnt(3downto0);
withhexselect
led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"1000000"when"0000",
"1111111"whenothers;
endrtl;
。
3、设计一个带计数使能、同步复位、同步装载的可逆七位二进制计数器,计数结果由共阴极七段数码管显示。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port(clk,clks,clr,en,stdl,dir:
instd_logic;
din:
instd_logic_vector(6downto0);
ledout:
outstd_logic_vector(6downto0);
scanout:
outstd_logic);
endcounter;
architectureaofcounteris
signalcnt:
std_logic_vector(6downto0);
signalhex:
std_logic_vector(3downto0);
signalled:
std_logic_vector(6downto0);
signalscan:
std_logic;
begin
process(clk)
begin
if(clk'eventandclk='1')then
ifclr='1'then
cnt<=(others=>'0');
elsifstdl='0'then
cnt<=din;
elsifen='1'then
ifdir='1'then
cnt<=cnt+'1';
else
cnt<=cnt-'1';
endif;
endif;
endif;
endprocess;
process(clks)
begin
if(clks'eventandclks='1')then
scan<=notscan;
endif;
endprocess;
scanout<=scan;
ledout<=notled;
hex<='0'&cnt(6downto4)whenscan='1'elsecnt(3downto0);
withhexselect
led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"0001000"when"1010",
"0000011"when"1011",
"1000110"when"1100",
"0100001"when"1101",
"0000110"when"1110",
"0001110"when"1111",
"1000000"whenothers;
enda;
4、设计一个带计数使能、异步复位、异步装载、可逆计数的通用计数器。
计数结果由共阴极七段数码管显示。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcounterIS
GENERIC(count_value:
INTEGER:
=9);
PORT(clk,clr,en,load,dir:
INSTD_LOGIC;
data_in:
ININTEGERRANGE0TOcount_value;
ledout:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDcounter;
ARCHITECTUREaOFcounterIS
SIGNALcnt:
INTEGERRANGE0TOcount_value;
SIGNALled:
STD_LOGIC_VECTOR(6DOWNTO0);
BEGIN
PROCESS(load,clk)
BEGIN
IFload='1'THEN
cnt<=data_in;
elsifclr='1'THEN
cnt<=0;
ELSIF(clk'EVENTANDclk='1')THEN
IFen='1'THEN
IFdir='1'THEN
IFcnt=count_valueTHEN
cnt<=0;
ELSE
cnt<=cnt+1;
endif;
else
IFcnt=0THEN
cnt<=count_value;
else
cnt<=cnt-1;
endif;
endif;
endif;
endif;
ENDPROCESS;
ledout<=NOTled;
WITHcntSELECT
led<="1111001"WHEN1,
"0100100"WHEN2,
"0110000"WHEN3,
"0011001"WHEN4,
"0010010"WHEN5,
"0000010"WHEN6,
"1111000"WHEN7,
"0000000"WHEN8,
"0010000"WHEN9,
"1000000"WHEN0,
"1111111"WHENothers;
ENDa;
5、设计一个具有16分频、8分频、4分频和2分频功能的分频器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdiv4IS
PORT(clk:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(3DOWNTO0);
fout:
OUTstd_LOGIC);
ENDdiv4;
ARCHITECTUREaOFdiv4IS
begin
process(clk)
variablecnt:
std_logic_vector(3downto0);
begin
if(clk'eventandclk='1')then
ifcnt="1111"then
cnt:
="0000";
else
cnt:
=cnt+'1';
endif;
ifdin="0000"then
fout<=cnt(3);
elsifdin="1000"then
fout<=cnt
(2);
elsifdin="1100"then
fout<=cnt
(1);
elsifdin="1110"then
fout<=cnt(0);
else
fout<='1';
endif;
endif;
endprocess;
enda;
6、设计一个正负脉宽相等的通用分频器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdivIS
GENERIC(num:
INTEGER:
=2);
PORT
(clk:
INSTD_LOGIC;
co:
OUTSTD_LOGIC);
ENDdiv;
ARCHITECTURErtlOFdivIS
BEGIN
PROCESS(clk)
VARIABLEcnt:
STD_LOGIC_VECTOR(numdownto0);
BEGIN
IF(clk'eventandclk='1')THEN
cnt:
=cnt+'1';
ENDIF;
co<=cnt(num);
ENDPROCESS;
ENDrtl;
7、设计一个正负脉宽可控的16分频的分频器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdivIS
PORT(clk:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(3DOWNTO0);
COUNT:
OUTSTD_LOGIC);
ENDdiv;
ARCHITECTURErtlOFdivIS
SIGNALco:
STD_LOGIC;
BEGIN
count<=co;
PROCESS(clk)
VARIABLEcnt:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
IF(clk'eventandclk='1')then
if(cnt="1111")then
cnt:
="0000";
co<=notco;
elsif(cnt=din)then
co<=notco;
cnt:
=cnt+'1';
else
cnt:
=cnt+'1';
endif;
endif;
endprocess;
endrtl;
8、根据需要设计一个分频器:
可以控制实现四种分频形式:
第一种:
8分频、第二种:
10分频、第三种:
15分频、第四种:
16分频,其中8分频和16分频为正负脉宽相等的分频器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port(clk:
instd_logic;
en:
instd_logic_vector(1downto0);
cout:
outstd_logic;
ledout:
outstd_logic_vector(6downto0));
endfenpin;
architecturedgnfenpinoffenpinis
signalled:
std_logic_vector(6downto0);
signalhex:
std_logic_vector(3downto0);
begin
process(clk)
variablecnt:
std_logic_vector(3downto0);
begin
if(clk'eventANDclk='1')then
if(en="00")then
if(cnt>="1000")then
cnt:
="0000";
else
cnt:
=cnt+'1';
endif;
cout<=cnt
(2);
elsif(en="01")then
if(cnt>="1010")then
cnt:
="0000";
cout<='1';
else
cnt:
=cnt+'1';
cout<='0';
endif;
elsif(en="10")then
if(cnt>="1110")then
cnt:
="0000";cout<='1';
else
cnt:
=cnt+'1';cout<='0';
endif;
else
if(cnt>="1111")then
cnt:
="0000";
else
cnt:
=cnt+'1';
endif;
cout<=cnt(3);
endif;
endif;
endprocess;
ledout<=notled;
withenselect
led<="0000000"when"00",
"0001000"when"01",
"0001110"when"10",
"1000000"when"11",
"1111111"whenothers;
enddgnfenpin;
9、设计一个M序列发生器,M序列为“11100111”(修改序列数原为1101101)
LIBRARYIEEE;
USEIEEE.STD_logic_1164.all;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYSEQIS
PORT(
CLK:
INSTD_logic;
FOUT:
OUTSTD_logic);
ENDSEQ;
ARCHITECTUREBEHAVEOFSEQIS
SIGNALCNT:
STD_logic_VECTOR(2DOWNTO0);
BEGIN
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFCNT="111"THEN
CNT<="000";
ELSE
CNT<=CNT+'1';
ENDIF;
ENDIF;
ENDPROCESS;
WITHCNTSELECT
FOUT<='1'WHEN"000",
'1'WHEN"001",
'1'WHEN"010",
'1'WHEN"011",
'0'WHEN"100",
'1'WHEN"101",
'0'WHEN"110",
'1'when"111",
'0'WHENOTHERS;
endBEHAVE;
10、设计一个彩灯控制器,彩灯共有21个,每次顺序点亮相邻的3个彩灯,如此循环执行,循环的方向可以控制(原为16个)
libraryieee;
useieee.std_logic_1164.all;
entitycaidengis
port(rl,clk:
instd_logic;
ledout:
outstd_logic_vector(15downto0));
endcaideng;
architectureaofcaidengis
signalled:
std_logic_vector(15downto0);
signalk:
std_logic;
begin
process(clk)
begin
if(clk'eventandclk='1')then
if(k='0')then
led<=(0=>'1',1=>'1',2=>'1',others=>'0');
k<='1';
elsif(rl='1')then
led<=led(14downto0)&led(15);
elsif(rl='0')then
led<=led(0)&led(15downto1);
endif;
endif;
ledout<=led;
endprocess;
enda;
11、设计一个具有左移、右移控制,同步并行装载和串行装载的8位串行移位寄存器,每次移位为1位
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYshifter1IS
PORT(clk,clr,ser,dir,stld:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(0TO7);
qh:
OUTSTD_LOGIC);
ENDshifter1;
ARCHITECTURErt1OFshifter1IS
SIGNALreg:
STD_LOGIC_VECTOR(0TO7);
begin
process(clk,clr)
begin
ifclr='1'then
reg<=(others=>'0');
elsifclk'eventandclk='1'then
ifstld='0'then
reg<=din;
else
if(dir='0')then
reg<=reg(1to7)&ser;qh<=reg(0);
else
reg<=ser®(0to6);qh<=reg(7);
endif;
endif;
endif;
endprocess;
endrt1;
12、设计一个15人表决电路,参加表决者为15人,同意为1,不同意为0,同意者过半则表决通过,绿指示灯亮,表决不通过则红指示灯亮。
数码管显示赞成人数。
(原来为7人)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityselectoris
port(b:
instd_logic_vector(6downto0);
clr:
instd_logic;
red,gree:
outstd_logic;
ledout:
outstd_logic_vector(6downto0));
endselector;
architecturertlofselectoris
signalled:
std_logic_v
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