ATMEGA12816AC.docx
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ATMEGA12816AC.docx
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ATMEGA12816AC
Features
•High-performance,Low-powerAVR®8-bitMicrocontroller
•AdvancedRISCArchitecture
–133PowerfulInstructions–MostSingleClockCycleExecution
–32x8GeneralPurposeWorkingRegisters+PeripheralControlRegisters
–FullyStaticOperation
–Upto16MIPSThroughputat16MHz
–On-chip2-cycleMultiplier
•NonvolatileProgramandDataMemories
–128KBytesofIn-SystemReprogrammableFlash
Endurance:
1,000Write/EraseCycles
–OptionalBootCodeSectionwithIndependentLockBits
In-SystemProgrammingbyOn-chipBootProgram
TrueRead-While-WriteOperation
–4KBytesEEPROM
Endurance:
100,000Write/EraseCycles
–4KBytesInternalSRAM
–Upto64KBytesOptionalExternalMemorySpace
–ProgrammingLockforSoftwareSecurity
–SPIInterfaceforIn-SystemProgramming
•JTAG(IEEEstd.1149.1Compliant)Interface
–Boundary-scanCapabilitiesAccordingtotheJTAGStandard
–ExtensiveOn-chipDebugSupport
–ProgrammingofFlash,EEPROM,FusesandLockBitsthroughtheJTAGInterface
•PeripheralFeatures
–Two8-bitTimer/CounterswithSeparatePrescalersandCompareModes
–TwoExpanded16-bitTimer/CounterswithSeparatePrescaler,CompareModeand
CaptureMode
–RealTimeCounterwithSeparateOscillator
–Two8-bitPWMChannels
–6PWMChannelswithProgrammableResolutionfrom2to16Bits
–OutputCompareModulator
–8-channel,10-bitADC
8Single-endedChannels
7DifferentialChannels
2DifferentialChannelswithProgrammableGainat1x,10x,or200x
–Byte-orientedTwo-wireSerialInterface
–DualProgrammableSerialUSARTs
–Master/SlaveSPISerialInterface
–ProgrammableWatchdogTimerwithOn-chipOscillator
–On-chipAnalogComparator
•SpecialMicrocontrollerFeatures
–Power-onResetandProgrammableBrown-outDetection
–InternalCalibratedRCOscillator
–ExternalandInternalInterruptSources
–SixSleepModes:
Idle,ADCNoiseReduction,Power-save,Power-down,Standby,
andExtendedStandby
–SoftwareSelectableClockFrequency
–ATmega103CompatibilityModeSelectedbyaFuse
–GlobalPull-upDisable
•I/OandPackages
–53ProgrammableI/OLines
–64-leadTQFP
•OperatingVoltages
–2.7-5.5VforATmega128L
–4.5-5.5VforATmega128
•SpeedGrades
–0-8MHzforATmega128L
–0-16MHzforATmega128
8-bit
Microcontroller
with128KBytes
In-System
Programmable
Flash
ShenzhenAngrandTechnologyLTD.
cn@
ATmega128
ATmega128L
Preliminary
Summary
Rev.2467CS–AVR–02/02
Note:
Thisisasummarydocument.Acompletedocumentis
availableonourwebsiteat.
1
PinConfigurations
Figure1.PinoutATmega128
PEN1
RXD0/(PDI)PE02
(TXD0/PDO)PE13
(XCK0/AIN0)PE24
(OC3A/AIN1)PE35
(OC3B/INT4)PE46
(OC3C/INT5)PE57
(T3/INT6)PE68
(IC3/INT7)PE79
(SS)PB010
(SCK)PB111
(MOSI)PB212
(MISO)PB313
(OC0)PB414
(OC1A)PB515
(OC1B)PB616
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA3(AD3)
PA4(AD4)
PA5(AD5)
PA6(AD6)
PA7(AD7)
PG2(ALE)
PC7(A15)
PC6(A14)
PC5(A13)
PC4(A12)
PC3(A11)
PC2(A10)
PC1(A9)
PC0(A8)
PG1(RD)
PG0(WR)
Overview
TheATmega128isalow-powerCMOS8-bitmicrocontrollerbasedontheAVR
enhancedRISCarchitecture.Byexecutingpowerfulinstructionsinasingleclockcycle,
theATmega128achievesthroughputsapproaching1MIPSperMHzallowingthesys-
temdesignertooptimizepowerconsumptionversusprocessingspeed.
2
ATmega128(L)
2467CS–AVR–02/02
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
(OC2/OC1C)PB7
TOSC2/PG3
TOSC1/1PG4
RESET
VCC
GND
XTAL2
XTAL1
(SCL/INT0)PD0
(SDA/INT1)PD1
(RXD1/INT2)PD2
(TXD1/INT3)PD3
(IC1)PD4
(XCK1)PD5
(T1)PD6
(T2)PD7
AVCC
GND
AREF
PF0(ADC0)
PF1(ADC1)
PF2(ADC2)
PF3(ADC3)
PF4(ADC4/TCK)
PF5(ADC5/TMS)
PF6(ADC6/TDO)
PF7(ADC7/TDI)
GND
VCC
PA0(AD0)
PA1(AD1)
PA2(AD2)
BlockDiagram
Figure2.BlockDiagram
ATmega128(L)
VCC
GND
PF0-PF7
PORTFDRIVERS
PA0-PA7
PORTADRIVERS
PC0-PC7
PORTCDRIVERS
DATAREGISTER
PORTF
DATADIR.
REG.PORTF
DATAREGISTER
PORTA
DATADIR.
REG.PORTA
DATAREGISTER
PORTC
DATADIR.
REG.PORTC
AVCC
AGND
AREF
PEN
JTAGTAP
ON-CHIPDEBUG
BOUNDARY-
SCAN
PROGRAMMING
LOGIC
USART0
DATAREGISTER
ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
DATADIR.
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
DATAREGISTER
8-BITDATABUS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCUCONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
SPI
DATADIR.DATAREGISTER
CALIB.OSC
OSCILLATOR
OSCILLATOR
TIMINGAND
CONTROL
USART1
DATADIR.
2-WIRESERIAL
INTERFACE
DATAREG.
DATADIR.
PORTE
REG.PORTE
PORTB
REG.PORTBPORTD
REG.PORTD
PORTG
REG.PORTG
2467CS–AVR–02/02
PORTEDRIVERS
PE0-PE7
PORTBDRIVERS
PB0-PB7
PORTDDRIVERS
PD0-PD7
PORTGDRIVERS
PG0-PG4
3
RESET
XT
AL1
XT
AL2
+
-
ANALOG
COMP
ARA
TOR
ATmega103and
ATmega128
Compatibility
TheAVRcorecombinesarichinstructionsetwith32generalpurposeworkingregisters.
Allthe32registersaredirectlyconnectedtotheArithmeticLogicUnit(ALU),allowing
twoindependentregisterstobeaccessedinonesingleinstructionexecutedinoneclock
cycle.Theresultingarchitectureismorecodeefficientwhileachievingthroughputsupto
tentimesfasterthanconventionalCISCmicrocontrollers.
TheATmega128providesthefollowingfeatures:
128KbytesofIn-SystemProgramma-
bleFlashwithRead-While-Writecapabilities,4KbytesEEPROM,4KbytesSRAM,53
generalpurposeI/Olines,32generalpurposeworkingregisters,RealTimeCounter
(RTC),fourflexibleTimer/CounterswithcomparemodesandPWM,2USARTs,abyte
orientedTwo-wireSerialInterface,an8-channel,10-bitADCwithoptionaldifferential
inputstagewithprogrammablegain,programmableWatchdogTimerwithInternalOscil-
lator,anSPIserialport,IEEEstd.1149.1compliantJTAGtestinterface,alsousedfor
accessingtheOn-chipDebugsystemandprogrammingandsixsoftwareselectable
powersavingmodes.TheIdlemodestopstheCPUwhileallowingtheSRAM,
Timer/Counters,SPIport,andinterruptsystemtocontinuefunctioning.ThePower-
downmodesavestheregistercontentsbutfreezestheOscillatorOscillator,disablingall
otherchipfunctionsuntilthenextinterruptorHardwareReset.InPower-savemode,the
asynchronoustimercontinuestorun,allowingtheusertomaintainatimerbasewhile
therestofthedeviceissleeping.TheADCNoiseReductionmodestopstheCPUand
allI/OmodulesexceptAsynchronousTimerandADC,tominimizeswitchingnoisedur-
ingADCconversions.InStandbymode,theCrystal/ResonatorOscillatorisrunning
whiletherestofthedeviceissleeping.Thisallowsveryfaststart-upcombinedwithlow
powerconsumption.InExtendedStandbymode,boththemainOscillatorandtheAsyn-
chronousTimercontinuetorun.
ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnology.
TheOn-chipISPFlashallowstheprogrammemorytobereprogrammedin-system
throughanSPIserialinterface,byaconventionalnonvolatilememoryprogrammer,or
byanOn-chipBootprogramrunningontheAVRcore.Thebootprogramcanuseany
interfacetodownloadtheapplicationprogramintheapplicationFlashmemory.Soft-
wareintheBootFlashsectionwillcontinuetorunwhiletheApplicationFlashsectionis
updated,providingtrueRead-While-Writeoperation.Bycombiningan8-bitRISCCPU
withIn-SystemSelf-ProgrammableFlashonamonolithicchip,theAtmelATmega128is
apowerfulmicrocontrollerthatprovidesahighlyflexibleandcosteffectivesolutionto
manyembeddedcontrolapplications.
TheATmega128AVRissupportedwithafullsuiteofprogramandsystemdevelopment
toolsincluding:
Ccompilers,macroassemblers,programdebugger/simulators,in-circuit
emulators,andevaluationkits.
TheATmega128isahighlycomplexmicrocontrollerwherethenumberofI/Olocations
supersedesthe64I/OlocationsreservedintheAVRinstructionset.Toensureback-
wardcompatibilitywiththeATmega103,allI/OlocationspresentinATmega103have
thesamelocationinATmega128.MostadditionalI/Olocationsareaddedinan
ExtendedI/Ospacestartingfrom$60to$FF,(i.e.,intheATmega103internalRAM
space).TheselocationscanbereachedbyusingLD/LDS/LDDandST/STS/STD
instructionsonly,notbyusingINandOUTinstructions.Therelocationoftheinternal
RAMspacemaystillbeaproblemforATmega103users.Also,theincreasednumberof
interruptvectorsmightbeaproblemifthecodeusesabsoluteaddresses.Tosolve
theseproblems,anATmega103compatibilitymodecanbeselectedbyprogramming
thefuseM103C.Inthismode,noneofthefunctionsintheExtendedI/Ospacearein
use,sotheinternalRAMislocatedasinATmega103.Also,theExtendedInterruptvec-
torsareremoved.
4
ATmega128(L)
2467CS–AVR–02/02
ATmega103Compatibility
Mode
PinDescriptions
VCC
GND
PortA(PA7..PA0)
PortB(PB7..PB0)
PortC(PC7..PC0)
2467CS–AVR–02/02
ATmega128(L)
TheATmega128is100%pincompatiblewithATmega103,andcanreplacethe
ATmega103oncurrentPrintedCircuitBoards.Theapplicationnote“Replacing
ATmeg
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