1、memory. These added function registers are the 16-bit X-, Y-, and Z-register,described later in this section.The ALU supports arithmetic and logic operations between registers or between a constantand a register. Single register operations can also be executed in the ALU. AfterFlashProgramMemoryInst
2、ructionRegisterDecoderCounterControl Lines32 x 8GeneralPurposeRegistrersALUStatusand ControlI/O LinesEEPROMData Bus 8-bitDataSRAMDirect AddressingIndirect AddressingInterruptUnitSPIWatchdogTimerAnalogComparatorI/O Module 2I/O Module1I/O Module n9ATmega16（L）2466NAVR10/06an arithmetic operation, the S
3、tatus Register is updated to reflect information about theresult of the operation.Program flow is provided by conditional and unconditional jump and call instructions,able to directly address the whole address space. Most AVR instructions have a single16-bit word format. Every program memory address
4、 contains a 16- or 32-bit instruction.Program Flash memory space is divided in two sections, the Boot program section andthe Application Program section. Both sections have dedicated Lock bits for write andread/write protection. The SPM instruction that writes into the Application Flash memorysectio
5、n must reside in the Boot Program section.During interrupts and subroutine calls, the return address Program Counter （PC） isstored on the Stack. The Stack is effectively allocated in the general data SRAM, andconsequently the Stack size is only limited by the total SRAM size and the usage of theSRAM
6、. All user programs must initialize the SP in the reset routine （before subroutinesor interrupts are executed）. The Stack Pointer SP is read/write accessible in the I/Ospace. The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.The memory
7、spaces in the AVR architecture are all linear and regular memory maps.A flexible interrupt module has its control registers in the I/O space with an additionalglobal interrupt enable bit in the Status Register. All interrupts have a separate interruptvector in the interrupt vector table. The interru
8、pts have priority in accordance with theirinterrupt vector position. The lower the interrupt vector address, the higher the priority.The I/O memory space contains 64 addresses for CPU peripheral functions as ControlRegisters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or
9、asthe Data Space locations following those of the Register File, $20 - $5F.ALU Arithmetic LogicThe high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, arithmetic operations betweengeneral purpose registers or between a
10、 register and an immediate are executed. TheALU operations are divided into three main categories arithmetic, logical, and bit-functions.Some implementations of the architecture also provide a powerful multipliersupporting both signed/unsigned multiplication and fractional format. See the “Instructi
11、onSet” section for a detailed description.Status Register The Status Register contains information about the result of the most recently executedarithmetic instruction. This information can be used for altering program flow in order toperform conditional operations. Note that the Status Register is
12、updated after all ALUoperations, as specified in the Instruction Set Reference. This will in many casesremove the need for using the dedicated compare instructions, resulting in faster andmore compact code.The Status Register is not automatically stored when entering an interrupt routine andrestored
13、 when returning from an interrupt. This must be handled by software.The AVR Status Register SREG is defined as:Bit 7 6 5 4 3 2 1 0I T H S V N Z C SREGRead/Write R/W R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 010 ATmega16（L） Bit 7 I: Global Interrupt EnableThe Global Interrupt Enable bit
14、must be set for the interrupts to be enabled. The individualinterrupt enable control is then performed in separate control registers. If the GlobalInterrupt Enable Register is cleared, none of the interrupts are enabled independent ofthe individual interrupt enable settings. The I-bit is cleared by
15、hardware after an interrupthas occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibitcan also be set and cleared by the application with the SEI and CLI instructions, asdescribed in the instruction set reference. Bit 6 T: Bit Copy StorageThe Bit Copy instructions BLD
16、（Bit LoaD） and BST （Bit STore） use the T-bit as source ordestination for the operated bit. A bit from a register in the Register File can be copiedinto T by the BST instruction, and a bit in T can be copied into a bit in a register in theRegister File by the BLD instruction. Bit 5 H: Half Carry Flag
17、The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry isuseful in BCD arithmetic. See the “Instruction Set Description” for detailed information. Bit 4 S: Sign Bit, S = N VThe S-bit is always an exclusive or between the Negative Flag N and the Twos ComplementOverflow
18、 Flag V. See the “Instruction Set Description” for detailed information. Bit 3 V: Twos Complement Overflow FlagThe Twos Complement Overflow Flag V supports twos complement arithmetics. Seethe “Instruction Set Description” for detailed information. Bit 2 N: Negative FlagThe Negative Flag N indicates
19、a negative result in an arithmetic or logic operation. See Bit 1 Z: Zero FlagThe Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the“Instruction Set Description” for detailed information. Bit 0 C: Carry FlagThe Carry Flag C indicates a carry in an arithmetic or logic ope
20、ration. See the “InstructionSet Description” for detailed information.11General PurposeRegister FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order toachieve the required performance and flexibility, the following input/output schemes aresupported by the Register F
21、ile: One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result inputFigure 4 shows the structure of the 32 general purpose working registers in the CPU
22、.Figure 4. AVR CPU General Purpose Working RegistersMost of the instructions operating on the Register File have direct access to all registers,and most of them are single cycle instructions.As shown in Figure 4, each register is also assigned a data memory address, mappingthem directly into the fir
23、st 32 locations of the user Data Space. Although not being physicallyimplemented as SRAM locations, this memory organization provides greatflexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set toindex any register in the file.7 0 Addr.R0 $00R1 $01R2 $02R13 $0DGene
24、ral R14 $0EPurpose R15 $0FWorking R16 $10Registers R17 $11R26 $1A X-register Low ByteR27 $1B X-register High ByteR28 $1C Y-register Low ByteR29 $1D Y-register High ByteR30 $1E Z-register Low ByteR31 $1F Z-register High Byte12 ATmega16（L）The X-register, Y-register andZ-registerThe registers R26.R31 h
25、ave some added functions to their general purpose usage.These registers are 16-bit address pointers for indirect addressing of the Data Space.The three indirect address registers X, Y, and Z are defined as described in Figure 5.Figure 5. The X-, Y-, and Z-registersIn the different addressing modes t
26、hese address registers have functions as fixed displacement,automatic increment, and automatic decrement （see the Instruction SetReference for details）.Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and forstoring return addresses after interrupts and subroutine calls. The Stack Pointer Registeralways points to the top of the Stack. Note that the Stack is implemented as growingfrom higher memory locations to lower memory locations. This implies that a Stac
