1、时钟周期,数据寄存器及相关电路,最快数据传递时间：时钟周期,在输入端添加控制电路，构成其他类型的触发器,D触发器的控制与扩展,数据寄存器及相关电路,数据寄存器及相关电路,D触发器的控制与扩展,并行寄存与移位寄存,数据寄存器及相关电路,多功能移位寄存器,数据寄存器及相关电路,第四章 算数逻辑单元,4.1 加法器4.2 乘法器,VHDL与数字集成电路设计,加法器设计,加法运算从最低位开始，逐步向高位进行；每一位相加时，产生1位结果（s），同时产生1位进位（c）；最低位相加时，只需要考虑2个数据的相加：半加；其余位相加时，需要考虑3个数据的相加：全加。,4.1 加法器、算数逻辑单元,加法器设计,半加
2、器,4.1 加法器、算数逻辑单元,加法器设计,全加器,4.2 加法器、算数逻辑单元,利用半加单元设计全加器,4.2 加法器、算数逻辑单元,可扩展的串行加法器：采用全加器级联构成,4.2 加法器、算数逻辑单元,4位串行加法器：ASIC设计 第1级采用半加；最高级取消进位。,4.2 加法器、算数逻辑单元,36,Full-Adder,37,The Binary Adder,38,Express Sum and Carry as a function of P,G,D,Define 3 new variable which ONLY depend on A,B,Generate（G）=AB,Propa
3、gate（P）=A,B,Delete=,A,B,Can also derive expressions for,S,and,C,o,based on,D and P,Propagate（P）=A,+,B,Note that we will be sometimes using an alternate definition for,39,The Ripple-Carry Adder,Worst case delay linear with the number of bits,Goal:Make the fastest possible carry path circuit,td=O（N）,t
4、adder=（N-1）tcarry+tsum,40,Complimentary Static CMOS Full Adder,28 Transistors,41,Inversion Property,42,Minimize Critical Path by Reducing Inverting Stages,Exploit Inversion Property,43,A Better Structure:The Mirror Adder,44,Transmission Gate Full Adder,45,Manchester Carry Chain,46,Manchester Carry C
5、hain,47,Carry-Bypass Adder,Also called Carry-Skip,48,Carry-Bypass Adder（cont.）,tadder=tsetup+Mtcarry+（N/M-1）tbypass+（M-1）tcarry+tsum,49,Carry Ripple versus Carry Bypass,50,Carry-Select Adder,51,Carry Select Adder:Critical Path,52,Linear Carry Select,53,Square Root Carry Select,54,LookAhead-Basic Ide
6、a,55,Look-Ahead:Topology,Expanding Lookahead equations:,All the way:,56,Logarithmic Look-Ahead Adder,57,Carry Lookahead Trees,Can continue building the tree hierarchically.,58,Tree Adders,16-bit radix-2 Kogge-Stone tree,59,Example:Domino Adder,Propagate,Generate,60,Example:Domino Adder,Propagate,Gen
7、erate,第四章算数逻辑单元,4.1 加法器4.2 乘法器,VHDL与数字集成电路设计,8位乘法器设计：基于基本单元的扩展设计,2位乘法器：由1位乘法结果相加而成,成本：4+4+4 门时间：1+3,4.3 数据累加与乘法器设计,8位乘法器设计：基于基本单元的扩展设计,4位乘法器：由2位乘法结果相加而成,4个2位乘法器并行运算，产生4组数据，然后进行相加。,4.3 数据累加与乘法器设计,65,The Binary Multiplication,66,The Array Multiplier,67,The MxN Array Multiplier Critical Path,Critical P
8、ath 1&2,68,Carry-Save Multiplier,69,Multiplier Floorplan,70,Wallace-Tree Multiplier,71,Wallace-Tree Multiplier,72,The Binary Shifter,73,The Barrel Shifter,Area Dominated by Wiring,74,4x4 barrel shifter,Widthbarrel 2 pm M,75,Logarithmic Shifter,76,0-7 bit Logarithmic Shifter,A,3,A,2,A,1,A,0,Out3,Out2,Out1,Out0,
