1、AVR CPU CoreIntroduction This section discusses the AVR core architecture in general. The main function of theCPU core is to ensure correct program execution. The CPU must therefore be able toaccess memories, perform calculations, control peripherals, and handle interrupts.Architectural Overview Fig
2、ure 3. Block Diagram of the AVR MCU ArchitectureIn order to maximize performance and parallelism, the AVR uses a Harvard architecture with separate memories and buses for program and data. Instructions in the programmemory are executed with a single level pipelining. While one instruction is being e
3、xecuted,the next instruction is pre-fetched from the program memory. This conceptenables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.The fast-access Register File contains 32 x 8-bit general purpose working registers witha single cloc
4、k cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)operation. In a typical ALU operation, two operands are output from the Register File,the operation is executed, and the result is stored back in the Register File in oneclock cycle.Six of the 32 registers can be used as three
5、16-bit indirect address register pointers forData Space addressing enabling efficient address calculations. One of the theseaddress pointers can also be used as an address pointer for look up tables in Flash Programmemory. These added function registers are the 16-bit X-, Y-, and Z-register,describe
6、d later in this section.The ALU supports arithmetic and logic operations between registers or between a constantand a register. Single register operations can also be executed in the ALU. AfterFlashProgramMemoryInstructionRegisterInstructionDecoderProgramCounterControl Lines32 x 8GeneralPurposeRegis
7、trersALUStatusand ControlI/O LinesEEPROMData Bus 8-bitDataSRAMDirect AddressingIndirect AddressingInterruptUnitSPIUnitWatchdogTimerAnalogComparatorI/O Module 2I/O Module1I/O Module n9ATmega16(L)2466NAVR10/06an arithmetic operation, the Status Register is updated to reflect information about theresul
8、t of the operation.Program flow is provided by conditional and unconditional jump and call instructions,able to directly address the whole address space. Most AVR instructions have a single16-bit word format. Every program memory address contains a 16- or 32-bit instruction.Program Flash memory spac
9、e is divided in two sections, the Boot program section andthe Application Program section. Both sections have dedicated Lock bits for write andread/write protection. The SPM instruction that writes into the Application Flash memorysection must reside in the Boot Program section.During interrupts and
10、 subroutine calls, the return address Program Counter (PC) isstored on the Stack. The Stack is effectively allocated in the general data SRAM, andconsequently the Stack size is only limited by the total SRAM size and the usage of theSRAM. All user programs must initialize the SP in the reset routine
11、 (before subroutinesor interrupts are executed). The Stack Pointer SP is read/write accessible in the I/Ospace. The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.The memory spaces in the AVR architecture are all linear and regular memor
12、y maps.A flexible interrupt module has its control registers in the I/O space with an additionalglobal interrupt enable bit in the Status Register. All interrupts have a separate interruptvector in the interrupt vector table. The interrupts have priority in accordance with theirinterrupt vector posi
13、tion. The lower the interrupt vector address, the higher the priority.The I/O memory space contains 64 addresses for CPU peripheral functions as ControlRegisters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or asthe Data Space locations following those of the Register File
14、, $20 - $5F.ALU Arithmetic LogicUnitThe high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, arithmetic operations betweengeneral purpose registers or between a register and an immediate are executed. TheALU operations
15、are divided into three main categories arithmetic, logical, and bit-functions.Some implementations of the architecture also provide a powerful multipliersupporting both signed/unsigned multiplication and fractional format. See the “InstructionSet” section for a detailed description.Status Register T
16、he Status Register contains information about the result of the most recently executedarithmetic instruction. This information can be used for altering program flow in order toperform conditional operations. Note that the Status Register is updated after all ALUoperations, as specified in the Instru
17、ction Set Reference. This will in many casesremove the need for using the dedicated compare instructions, resulting in faster andmore compact code.The Status Register is not automatically stored when entering an interrupt routine andrestored when returning from an interrupt. This must be handled by
18、software.The AVR Status Register SREG is defined as:Bit 7 6 5 4 3 2 1 0I T H S V N Z C SREGRead/Write R/W R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 010 ATmega16(L)2466NAVR10/06 Bit 7 I: Global Interrupt EnableThe Global Interrupt Enable bit must be set for the interrupts to be enabled.
19、The individualinterrupt enable control is then performed in separate control registers. If the GlobalInterrupt Enable Register is cleared, none of the interrupts are enabled independent ofthe individual interrupt enable settings. The I-bit is cleared by hardware after an interrupthas occurred, and i
20、s set by the RETI instruction to enable subsequent interrupts. The Ibitcan also be set and cleared by the application with the SEI and CLI instructions, asdescribed in the instruction set reference. Bit 6 T: Bit Copy StorageThe Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit a
21、s source ordestination for the operated bit. A bit from a register in the Register File can be copiedinto T by the BST instruction, and a bit in T can be copied into a bit in a register in theRegister File by the BLD instruction. Bit 5 H: Half Carry FlagThe Half Carry Flag H indicates a Half Carry i
22、n some arithmetic operations. Half Carry isuseful in BCD arithmetic. See the “Instruction Set Description” for detailed information. Bit 4 S: Sign Bit, S = N VThe S-bit is always an exclusive or between the Negative Flag N and the Twos ComplementOverflow Flag V. See the “Instruction Set Description”
23、 for detailed information. Bit 3 V: Twos Complement Overflow FlagThe Twos Complement Overflow Flag V supports twos complement arithmetics. Seethe “Instruction Set Description” for detailed information. Bit 2 N: Negative FlagThe Negative Flag N indicates a negative result in an arithmetic or logic op
24、eration. Seethe “Instruction Set Description” for detailed information. Bit 1 Z: Zero FlagThe Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the“Instruction Set Description” for detailed information. Bit 0 C: Carry FlagThe Carry Flag C indicates a carry in an arithmetic
25、 or logic operation. See the “InstructionSet Description” for detailed information.11ATmega16(L)2466NAVR10/06General PurposeRegister FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order toachieve the required performance and flexibility, the following input/output s
26、chemes aresupported by the Register File: One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result inputFigure 4 shows the structure of the 32 general
27、 purpose working registers in the CPU.Figure 4. AVR CPU General Purpose Working RegistersMost of the instructions operating on the Register File have direct access to all registers,and most of them are single cycle instructions.As shown in Figure 4, each register is also assigned a data memory addre
28、ss, mappingthem directly into the first 32 locations of the user Data Space. Although not being physicallyimplemented as SRAM locations, this memory organization provides greatflexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set toindex any register in the file.7
29、 0 Addr.R0 $00R1 $01R2 $02R13 $0DGeneral R14 $0EPurpose R15 $0FWorking R16 $10Registers R17 $11R26 $1A X-register Low ByteR27 $1B X-register High ByteR28 $1C Y-register Low ByteR29 $1D Y-register High ByteR30 $1E Z-register Low ByteR31 $1F Z-register High Byte12 ATmega16(L)2466NAVR10/06The X-registe
30、r, Y-register andZ-registerThe registers R26.R31 have some added functions to their general purpose usage.These registers are 16-bit address pointers for indirect addressing of the Data Space.The three indirect address registers X, Y, and Z are defined as described in Figure 5.Figure 5. The X-, Y-,
31、and Z-registersIn the different addressing modes these address registers have functions as fixed displacement,automatic increment, and automatic decrement (see the Instruction SetReference for details).Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and forstoring return addresses after interrupts and subroutine calls. The Stack Pointer Registeralways points to the top of the Stack. Note that the Stack is implemented as growingfrom higher memory locations to lower memory locations. This implies that a Stac
