1、学生姓名 吴秀 学生学号 _ 200803021005 专业班级 _ 信息08- 1 指导教师 贺爱玲 二一二 年 五 月 七 日外文资料出处：AT89C51 MicrocomputerAt present, as a bus passengers largest public transport, safety and comfort has a bearing on the vital interests of the majority of the people. However, the management and bus services have been a number of
2、 loopholes. In addition to the driver to drive, be responsible for manually stop and open the door, attention has been distributed, easy to traffic accidents. The driver while driving should be road observation, the number of passengers of the bus can not be real-time monitoring. At the same time, t
3、he company provides public transportation bus driver can not refuse, to work the peak of the high aspirations of the passenger bus, bus overload situation occurs from time to time, together with the norms and get off on the low awareness, the accident prone, very dangerous. In a moving bus, the bus
4、companies it is difficult for the bus in real-time management, which is hard to avoid the occurrence of speeding bus, a serious threat to the safety of the passengers. Station passengers know the difficulties in travel due to the easy way and do not see too many passengers stand or get off on the st
5、range point and missed the station, time is not clear and in-bus temperature, may also couse stolen when the passenger take out the cell phone to see what time is it.Everything above led to a low comfort of the bus. In view of this, based on RFID technology, multi-functional automatic stop system de
6、sign methods have been put forward. RFID （Radio Frequency Identification, that is, radio frequency identification technology） automatically stop Multi-functional system features include: automatic identification bus stations, auto-stop voice, LED dot matrix screen showed real-time information, direc
7、tion show up and down, show time, temperature Showed that the bus station automatically open the door, show the speed, speed warning, the bus show that the number of passengers to get off on the norms of management, such as overloading warning function of human nature, the real driver to reduce the
8、burden of increased traffic safety. The system is cost-effective and can improve the public transport operators service quality, with a certain degree of market applications.The improtant part for bus is radio frequency identification and it is used AT89C51 microcomputer to fill its functions.The ou
9、tline of the AT89C51 as listed below.1、Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory （PEROM）. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible wit
10、h the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer wh
11、ich provides a highly-flexible and cost-effective solution to many embedded control applications.2、Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture
12、, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port an
13、d interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.3、引脚描述Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an ou
14、tput port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port
15、 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during programverification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.W
16、hen 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current （IIL） because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and
17、 verification.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being p
18、ulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During acce
19、sses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pul
20、lups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current （IIL） because of the pullups.Port 3 also serves the
21、 functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pul
22、se for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input （PROG） during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. No
23、te, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disa
24、ble bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped
25、 during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on re
26、set.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage（VPP） during Flash programming, for parts that require12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Ou
27、tput from the inverting oscillator amplifier.4、Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive
28、the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and max
29、imum voltage high and low time specifications must be observed.5、Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mo
30、de. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control.
31、On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a por
32、t pin or to external memory.6、Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level a
