1、Verilog HDL 6位数码管扫描驱动汇总Verilog HDL 6位数码管扫描驱动生成0-999999的数字用于显示 module DIGIT_CREATE_MODULE(CLK,RST,Number);input CLK,RST;output19:0 Number;reg22:0 rCLK_DIV;reg19:0 rNumber;always (posedge CLK or negedge RST)if(!RST)beginrCLK_DIV=22D0;rNumber=20D0;endelse if(rCLK_DIV=22D4999999)beginrCLK_DIV=22D0;if(rN
2、umber=20D999999) rNumber=20D0; else rNumber=rNumber+1B1;endelserCLK_DIV=rCLK_DIV+1B1;assign Number=rNumber;endmodule数码管驱动module DIGIT_MODULE(CLK,RST,DIG,SEL,BCD0,BCD1,BCD2,BCD3,BCD4,BCD5);input CLK,RST;output7:0 DIG;output5:0 SEL;input3:0 BCD0,BCD1,BCD2,BCD3,BCD4,BCD5;parameter N0 = 8B11000000, N1 =
3、 8b11111001, N2 = 8b10100100, N3 = 8b10110000, N4 = 8b10011001,N5 = 8B10010010, N6 = 8b10000010, N7 = 8b11111000, N8 = 8b10000000, N9 = 8b10010000;reg7:0 rD0,rD1,rD2,rD3,rD4,rD5;always (posedge CLK or negedge RST)if(!RST)beginrD0=N0;rD1=N0;rD2=N0;rD3=N0;rD4=N0;rD5=N0;endelsebegincase(BCD0)4D0: rD0=N
4、0;4D1: rD0=N1;4D2: rD0=N2;4D3: rD0=N3;4D4: rD0=N4;4D5: rD0=N5;4D6: rD0=N6;4D7: rD0=N7;4D8: rD0=N8;4D9: rD0=N9;default: rD0=N0;endcase;case(BCD1)4D0: rD1=N0;4D1: rD1=N1;4D2: rD1=N2;4D3: rD1=N3;4D4: rD1=N4;4D5: rD1=N5;4D6: rD1=N6;4D7: rD1=N7;4D8: rD1=N8;4D9: rD1=N9;default: rD1=N0;endcase;case(BCD2)4D
5、0: rD2=N0;4D1: rD2=N1;4D2: rD2=N2;4D3: rD2=N3;4D4: rD2=N4;4D5: rD2=N5;4D6: rD2=N6;4D7: rD2=N7;4D8: rD2=N8;4D9: rD2=N9;default: rD2=N0;endcase;case(BCD3)4D0: rD3=N0;4D1: rD3=N1;4D2: rD3=N2;4D3: rD3=N3;4D4: rD3=N4;4D5: rD3=N5;4D6: rD3=N6;4D7: rD3=N7;4D8: rD3=N8;4D9: rD3=N9;default: rD3=N0;endcase;case
6、(BCD4)4D0: rD4=N0;4D1: rD4=N1;4D2: rD4=N2;4D3: rD4=N3;4D4: rD4=N4;4D5: rD4=N5;4D6: rD4=N6;4D7: rD4=N7;4D8: rD4=N8;4D9: rD4=N9;default: rD4=N0;endcase;case(BCD5)4D0: rD5=N0;4D1: rD5=N1;4D2: rD5=N2;4D3: rD5=N3;4D4: rD5=N4;4D5: rD5=N5;4D6: rD5=N6;4D7: rD5=N7;4D8: rD5=N8;4D9: rD5=N9;default: rD5=N0;endc
7、ase;endreg11:0 rCLK_DIV;always (negedge CLK or negedge RST)if(!RST)rCLK_DIV=12D0;else if(rCLK_DIV=12D3599)rCLK_DIV=12D0;elserCLK_DIV=rCLK_DIV+1B1;reg5:0 rSEL;reg7:0 rDIG;always (negedge CLK or negedge RST)if(!RST)beginrSEL=6B111111;rDIG=N0;endelse if(rCLK_DIV=12D0)beginrSEL=6B111110;rDIG=rD5;endelse
8、 if(rCLK_DIV=12D600)beginrSEL=6B111101;rDIG=rD4;endelse if(rCLK_DIV=12D1200)beginrSEL=6B111011;rDIG=rD3;endelse if(rCLK_DIV=12D1800)beginrSEL=6B110111;rDIG=rD2;endelse if(rCLK_DIV=12D2400)beginrSEL=6B101111;rDIG=rD1;endelse if(rCLK_DIV=12D3000)beginrSEL=6B011111;rDIG=rD0;endassign DIG=rDIG;assign SE
9、L=rSEL;endmodule20bit二进制转BCD码module BIN_TO_BCD_MODULE(BIN,BCD0,BCD1,BCD2,BCD3,BCD4,BCD5);parameter BIT_WIDTH=20;input BIT_WIDTH-1:0 BIN;output 3:0 BCD0,BCD1,BCD2,BCD3,BCD4,BCD5;function3:0 LSA3;input 3:0 IN;case (IN)4B0000: LSA3 = 4B0000;4B0001: LSA3 = 4B0001;4B0010: LSA3 = 4B0010;4B0011: LSA3 = 4B0
10、011;4B0100: LSA3 = 4B0100;4B0101: LSA3 = 4B1000;4B0110: LSA3 = 4B1001;4B0111: LSA3 = 4B1010;4B1000: LSA3 = 4B1011;4B1001: LSA3 = 4B1100;default: LSA3 = 4B0000;endcaseendfunctionwire 3:0 wA1:BIT_WIDTH-3;wire 3:0 wB1:BIT_WIDTH-3;assign wA1=1B0,BINBIT_WIDTH-1:BIT_WIDTH-3;assign wB1=LSA3(wA1);genvar gB;
11、generate for(gB=2;gB=BIT_WIDTH-3;gB=gB+1)begin : CAassign wAgB=wBgB-12:0,BINBIT_WIDTH-gB-2;assign wBgB=LSA3(wAgB);endendgeneratewire 3:0 wC1:BIT_WIDTH-6;wire 3:0 wD1:BIT_WIDTH-6;assign wC1=1B0,wB13,wB23,wB33;assign wD1=LSA3(wC1);genvar gD;generate for(gD=2;gD=BIT_WIDTH-6;gD=gD+1)begin : CBassign wCg
12、D=wDgD-12:0,wBgD+23;assign wDgD=LSA3(wCgD);endendgeneratewire 3:0 wE1:BIT_WIDTH-9;wire 3:0 wF1:BIT_WIDTH-9;assign wE1=1B0,wD13,wD23,wD33;assign wF1=LSA3(wE1);genvar gF;generate for(gF=2;gF=BIT_WIDTH-9;gF=gF+1)begin :CCassign wEgF=wFgF-12:0,wDgF+23;assign wFgF=LSA3(wEgF);endendgeneratewire 3:0 wG1:BI
13、T_WIDTH-12;wire 3:0 wH1:BIT_WIDTH-12;assign wG1=1B0,wF13,wF23,wF33;assign wH1=LSA3(wG1);genvar gH;generate for(gH=2;gH=BIT_WIDTH-12;gH=gH+1)begin :CDassign wGgH=wHgH-12:0,wFgH+23;assign wHgH=LSA3(wGgH);endendgeneratewire 3:0 wI1:BIT_WIDTH-15;wire 3:0 wJ1:BIT_WIDTH-15;assign wI1=1B0,wH13,wH23,wH33;as
14、sign wJ1=LSA3(wI1);genvar gJ;generate for(gJ=2;gJ=BIT_WIDTH-15;gJ=gJ+1)begin :CEassign wIgJ=wJgJ-12:0,wHgJ+23;assign wJgJ=LSA3(wIgJ);endendgeneratewire 3:0 wK1:BIT_WIDTH-18;wire 3:0 wL1:BIT_WIDTH-18;assign wK1=1B0,wJ13,wJ23,wJ33;assign wL1=LSA3(wK1);genvar gL;generate for(gL=2;gL=BIT_WIDTH-18;gL=gL+
15、1)begin :CFassign wKgL=wLgL-12:0,wJgL+23;assign wLgL=LSA3(wKgL);endendgenerateassign BCD0=wBBIT_WIDTH-32:0,BIN0;assign BCD1=wDBIT_WIDTH-62:0,wBBIT_WIDTH-33;assign BCD2=wFBIT_WIDTH-92:0,wDBIT_WIDTH-63;assign BCD3=wHBIT_WIDTH-122:0,wFBIT_WIDTH-93;assign BCD4=wJBIT_WIDTH-152:0,wHBIT_WIDTH-123;assign BCD5=wLBIT_WIDTH-182:0,wJBIT_WIDTH-153;endmodule
