1、 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY first ISPORT （ clk : IN std_logic; rst : c : OUT std_logic_vector（7 DOWNTO 0） ）;END first;ARCHITECTURE arch OF first IS CONSTANT state0 : std_logic_vector（2 DOWNTO 0） := 000; CONSTANT state1
2、 :001 CONSTANT state2 :010 CONSTANT state3 :011 CONSTANT state4 :100 CONSTANT state5 :101 CONSTANT state6 :110 CONSTANT state7 :111 SIGNAL state : std_logic_vector（2 DOWNTO 0）; SIGNAL cnt :BEGIN PROCESS（clk,rst） BEGIN IF （NOT rst = 1） THEN state = state0; cnt = state1; WHEN state1 = state2; WHEN sta
3、te2 = state3; WHEN state3 = state4; WHEN state4 = state5; WHEN state5 = state6; WHEN state6 = state7; WHEN state7 = WHEN OTHERS =NULL; END CASE; END IF; END PROCESS; PROCESS（state） BEGIN CASE state IS c 1010101001010101END arch;3.2 library IEEE;ENTITY second IS PORT （ ）;END second;ARCHITECTURE arch
4、OF second IS10000000010000000010000000010000000010000000010000000010000000013.3ENTITY third ISEND third;ARCHITECTURE arch OF third ISNULL3.4 library ieee;use ieee.std_logic_1164.all;entity sanba isport（a,b,c:in std_logic; y7,y6,y5,y4,y3,y2,y1,y0:out std_logic）;end entity sanba;architecture behav of sanba issignal abc: std_logic_vector（2 downto 0）;beginabc y0=0y1y2y3y4y5y6y7 end case; end process;end architecture behav;3.5 library IEEE;1100000001100000 c 00110000000110000000110000000110000000113.6 library IEEE;
