1、基于超声波检测的倒车雷达设计硬件设计 中英文献 精品 2007 级毕业（设计）论文 信息工程学院 系（院） 电子信息工程 专业 中英文献翻译 题 目 基于超声波检测的倒车雷达设计（硬件设计） 学 生 姓 名 班 级 2007电子信息工程 学 号 指 导 教 师 日 期 2011 年 03 月 21 日 教 务 处 订 制AT89C2051 Microcontroller Instructions1.1 Features Compatible with MCS-51 Products 2 Kbytes of Reprogrammable Flash MemoryEndurance: 1,000
2、Write/Erase Cycles 2.7 V to 6 V Operating Range Fully Static Operation: 0 Hz to 24 MHz Two-Level Program Memory Lock 128 x 8-Bit Internal RAM 15 Programmable I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources Programmable Serial UART Channel Direct LED Drive Outputs On-Chip Analog Comparator
3、Low Power Idle and Power Down Modes1.2 DescriptionThe AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 2 Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high density nonvolatile memory technology and is compatible
4、with the industry standard MCS-51 instruction set and pinout. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.The AT89C2051 provides
5、the following standard features: 2 Kbytes of Flash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C2051 is designed with
6、 static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscilla
7、tor disabling all other chip functions until the next hardware reset.1.3 Pin Configuration 1.4 Pin DescriptionVCC Supply voltage.GND Ground.Port 1Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also ser
8、ve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as in
9、puts and are externally pulled low, they will source current (IIL) because of the internal pullups.Port 1 also receives code data during Flash programming and program verification.Port 3Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O pins with internal pullups. P3.6 is hard-wired as an in
10、put to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled
11、 low will source current (IIL) because of the pullups. Port Pin Alternate FunctionsP3.0RXD (serial input port)P3.1TXD (serial output port)P3.2INT0 (external interrupt 0)P3.3INT1 (external interrupt 1)P3.4T0 (timer 0 external input)P3.5T1 (timer 1 external input)Port 3 also serves the functions of va
12、rious special features of the AT89C2051 as listed below:1.5 Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be
13、used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divideby-two flip-flop, but
14、minimum and maximum voltage high and low time specifications must be observed.1.6 Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shown in the table below. Note that not all of the addresses are occupied, and unoccupied addresses may not
15、 be implemented on the chip. Read accesses. to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea tures. In that case, the
16、reset or inactive values of the new bits will always be 0.1.7 Restrictions on Certain InstructionsThe AT89C2051 and is an economical and cost-effective member of Atmels growing family of microcontrollers. It contains 2 Kbytes of flash program memory. It is fully compatible with the MCS-51 architectu
17、re, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device.All the instructions related to jumping or branching should be restricted such that the destination address falls withi
18、n the physical program memory space of the device, which is 2K for the AT89C2051. This should be the responsibility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89C2051 (with 2K of memory), whereas LJMP 900H would not.1. Branching instructions:LCALL, LJMP
19、, ACALL, AJMP, SJMP, JMP A+DPTRThese unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to 7FFH for the 89C2051). Violating the p
20、hysical space limits may cause unknown program behavior.CJNE ., DJNZ ., JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same rule above applies. Again, violating the memory boundaries may cause erratic execution.For applications involving interrupts the normal interr
21、upt service routine address locations of the 80C51 family architecture have been preserved.2. MOVX-related instructions, Data Memory:The AT89C2051 contains 128 bytes of internal data memory. Thus, in the AT89C2051 the stack depth is limited to 128 bytes, the amount of available RAM. External DATA me
22、mory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX . instructions should be included in the program.A typical 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the
23、responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly.1.8 Program Memory Lock BitsOn the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional
24、 features listed in the table below:Lock Bit Protection Modes(1) Program Lock BitsLB1LB2Protection Type1UUNo program lock features.2PUFurther programming of theFlash is disabled.3PPSame as mode 2, also verifyis disabled.Note: 1. The Lock Bits can only be erased with the Chip Erase operation1.9 Idle
25、ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a
26、hardware reset.P1.0 and P1.1 should be set to 0 if no external pullups are used, or set to 1 if external pullups are used.It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the in
27、ternal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle
28、should not be one that writes to a port pin or to external memory.1.10 Power Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power dow
29、n mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and sta
30、bilize.P1.0 and P1.1 should be set to 0 if no external pullups are used, or set to 1 if external pullups are used.1.11 Programming The FlashThe AT89C2051 is shipped with the 2 Kbytes of on-chip PEROM code memory array in the erased state (i.e., contents = FFH) and ready to be programmed. The code me
31、mory array is programmed one byte at a time. Once the array is programmed, to re-program any non-blank byte, the entire memory array needs to be erased electrically.Internal Address Counter: The AT89C2051 contains an internal PEROM address counter which is always reset to 000H on the rising edge of
32、RST and is advanced by applying a positive going pulse to pin XTAL1.Programming Algorithm: To program the AT89C2051, the following sequence is recommended.1. Power-up sequence:Apply power between VCC and GND pins Set RST and XTAL1 to GNDWith all other pins floating, wait for greater than 10 milliseconds2. Set pin RST to H Set pin P3.2 to H3. Apply the appropriate combination of H or L
