1、数字逻辑电路课程设计4B5B编码VHDL实现含完整代码Word版电 子 科 技 大 学UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA数字逻辑设计实验报告实验题目: 4B5B编码器 学生姓名: 指导老师: 一、实验内容4B/5B编码是百兆以太网中线路层编码类型之一,该试验需要实现用5bit的二进制数来表示4bit二进制数。二、实验要求1、功能性要求: 能够实现4B5B编码,即输入4bit数据时能输出正确的5bit编码结果。2、算法要求: 利用卡诺图对编码真值表进行化简,得出其逻辑表达式,并基于此进行硬件设计。3、设计性要求:使用代
2、码及原理图两种设计方式来进行设计。采用基本门结构化描述。能够编写Test Bench文件,并利用Modelsim进行仿真。三、实验原理及设计思路1、实验原理:在IEEE 802.9a等时以太网标准中的4B:5B编码方案,因其效率高和容易实现而被采用。这种编码的特点是将欲发送的数据流每4bit作为一个组,然后按照4B/5B编码规则将其转换成相应5bit码。5bit码共有32种组合,但只采用其中的16种对应4bit码的16种,其他的16种或者未用或者用作控制码,以表示帧的开始和结束、光纤线路的状态(静止、空闲、暂停)等。4B5B编码表如下:2、设计思路:(1)整体思路: 对已知的编码真值表,首先利
3、用卡诺图对其进行化简,得出其逻辑表达式,再用基本门结构将其实现。(2)卡诺图与表达式: 设输入的4位编码为:ABCD,输出的5位编码为:VWXYZ,则分别画出其卡诺图并得出表达式如下:1.V:V=A+BD+BC2.W:W=B+AC3.X:X=C+ABD4.Y:Y=AB+AB+CD+AC5.Z:Z=D(3)基本门结构设计: 由上述表达式可见,用到的基本门有:非门、2输入与门、3输入与门、2输入或门、3输入或门、4输入或门,用not、and、or将其一一表示出即可。四、程序设计1、顶层模块:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity main i
4、s Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; v : out STD_LOGIC; w : out STD_LOGIC; x : out STD_LOGIC; y : out STD_LOGIC; z : out STD_LOGIC);end main;architecture Behavioral of main is COMPONENT noti PORT( i : IN std_logic; o : OUT std_logic ); END COMPONENT; COMPO
5、NENT and2i PORT( i1 : IN std_logic; i2 : IN std_logic; o : OUT std_logic ); END COMPONENT; COMPONENT and3i PORT( i1 : IN std_logic; i2 : IN std_logic; i3 : IN std_logic; o : OUT std_logic ); END COMPONENT; COMPONENT or2i PORT( i1 : IN std_logic; i2 : IN std_logic; o : OUT std_logic ); END COMPONENT;
6、 COMPONENT or3i PORT( i1 : IN std_logic; i2 : IN std_logic; i3 : IN std_logic; o : OUT std_logic ); END COMPONENT; COMPONENT or4i PORT( i1 : IN std_logic; i2 : IN std_logic; i3 : IN std_logic; i4 : IN std_logic; o : OUT std_logic ); END COMPONENT; signal nota,notb,notc,notd,v1,v2,v3,w1,w2,x1,x2,y1,y
7、2,y3,y4,vv,ww,xx,yy,zz : std_logic;begin-not- Inst_noti_nota: noti PORT MAP( i = a, o = nota ); Inst_noti_notb: noti PORT MAP( i = b, o = notb ); Inst_noti_notc: noti PORT MAP( i = c, o = notc ); Inst_noti_notd: noti PORT MAP( i = d, o = notd ); -v- v1 notb, i2 = notd, o = v2 ); Inst_and2i_v3: and2i
8、 PORT MAP( i1 = notb, i2 = c, o = v3 ); Inst_or3i_vv: or3i PORT MAP( i1 = v1, i2 = v2, i3 = v3, o = vv ); -w- w1 nota, i2 = notc, o = w2 ); Inst_or2i_ww: or2i PORT MAP( i1 = w1, i2 = w2, o = ww ); -x- x1 nota, i2 = notb, i3 = notd, o = x2 ); Inst_or2i_xx: or2i PORT MAP( i1 = x1, i2 = x2, o = xx );-y
9、- Inst_and2i_y1: and2i PORT MAP( i1 = nota, i2 = b, o = y1 ); Inst_and2i_y2: and2i PORT MAP( i1 = a, i2 = notb, o = y2 ); Inst_and2i_y3: and2i PORT MAP( i1 = notc, i2 = notd, o = y3 ); Inst_and2i_y4: and2i PORT MAP( i1 = a, i2 = notc, o = y4 ); Inst_or4i_yy: or4i PORT MAP( i1 = y1, i2 = y2, i3 = y3,
10、 i4 = y4, o = yy ); -z- zz vv, o = v ); Inst_noti_w: noti PORT MAP( i = ww, o = w ); Inst_noti_x: noti PORT MAP( i = xx, o = x ); Inst_noti_y: noti PORT MAP( i = yy, o = y ); Inst_noti_z: noti PORT MAP( i = zz, o = z ); end Behavioral;2、非门:entity noti is Port ( i : in STD_LOGIC; o : out STD_LOGIC);e
11、nd noti;architecture Behavioral of noti isbegino = not i;end Behavioral;3、2输入与门:entity and2i is Port ( i1 : in STD_LOGIC; i2 : in STD_LOGIC; o : out STD_LOGIC);end and2i;architecture Behavioral of and2i isbegino = i1 and i2;end Behavioral;4、3输入与门:entity and3i is Port ( i1 : in STD_LOGIC; i2 : in STD
12、_LOGIC; i3 : in STD_LOGIC; o : out STD_LOGIC);end and3i;architecture Behavioral of and3i isbegino=i1 and i2 and i3;end Behavioral;5、2输入或门:entity or2i is Port ( i1 : in STD_LOGIC; i2 : in STD_LOGIC; o : out STD_LOGIC);end or2i;architecture Behavioral of or2i isbegino=i1 or i2;end Behavioral;6、3输入或门:e
13、ntity or3i is Port ( i1 : in STD_LOGIC; i2 : in STD_LOGIC; i3 : in STD_LOGIC; o : out STD_LOGIC);end or3i;architecture Behavioral of or3i isbegino = i1 or i2 or i3;end Behavioral;7、4输入或门:entity or4i is Port ( i1 : in STD_LOGIC; i2 : in STD_LOGIC; i3 : in STD_LOGIC; i4 : in STD_LOGIC; o : out STD_LOG
14、IC);end or4i;architecture Behavioral of or4i isbegino=i1 or i2 or i3 or i4;end Behavioral;五、仿真与硬件调试1、仿真:(1)顶层仿真:1.仿真文件:LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY test1 ISEND test1; ARCHITECTURE behavior OF test1 IS - Component Declaration for the Unit Under Test (UUT) COMPONENT main PORT( a : I
15、N std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; v : OUT std_logic; w : OUT std_logic; x : OUT std_logic; y : OUT std_logic; z : OUT std_logic ); END COMPONENT; -Inputs signal a : std_logic := 0; signal b : std_logic := 0; signal c : std_logic := 0; signal d : std_logic := 0; -Outp
16、uts signal v : std_logic; signal w : std_logic; signal x : std_logic; signal y : std_logic; signal z : std_logic; - No clocks detected in port list. Replace below with - appropriate port name BEGIN - Instantiate the Unit Under Test (UUT) uut: main PORT MAP ( a = a, b = b, c = c, d = d, v = v, w = w,
17、 x = x, y = y, z = z ); - Stimulus process stim_proc: process begin a=0;b=0;c=0;d=0; wait for 100 ns; a=0;b=0;c=0;d=1; wait for 100 ns; a=0;b=0;c=1;d=0; wait for 100 ns; a=0;b=0;c=1;d=1; wait for 100 ns; a=0;b=1;c=0;d=0; wait for 100 ns; a=0;b=1;c=0;d=1; wait for 100 ns; a=0;b=1;c=1;d=0; wait for 10
18、0 ns; a=0;b=1;c=1;d=1; wait for 100 ns; a=1;b=0;c=0;d=0; wait for 100 ns; a=1;b=0;c=0;d=1; wait for 100 ns; a=1;b=0;c=1;d=0; wait for 100 ns; a=1;b=0;c=1;d=1; wait for 100 ns; a=1;b=1;c=0;d=0; wait for 100 ns; a=1;b=1;c=0;d=1; wait for 100 ns; a=1;b=1;c=1;d=0; wait for 100 ns; a=1;b=1;c=1;d=1; - ins
19、ert stimulus here wait; end process;END;2.仿真结果:(2)非门仿真:(3)2输入与门仿真:(4)2输入或门仿真:(5)3输入或门仿真:(6)4输入或门仿真:2、硬件调试:(1)管脚配置:NET a LOC = P6; #sb1NET b LOC = P141;NET c LOC = P136;NET d LOC = P129;NET v LOC = P122;NET w LOC = P123;NET x LOC = P124;NET y LOC = P125;NET z LOC = P126;(2)调试结果: 如上图所示,4B码为“0000”,其对应的5B码为“11110”。 如上图所示,4B码为“1100”,其对应的5B码为“11010”。六、结束语这次实验是我第一次用VHDL编写程序,并对其进行仿真和硬件调试。虽然这个实验很简单,但是在此过程中我还是有所收获,其中让我收获最大的就是使我在编程时脑海中开始有了“器件描述”的思想,使自己原本脑海中C语言的实现换成了实在的对电路器件与功能的描述。并且感谢同学及老师在试验中的帮助! 友情提示:本资料代表个人观点,如有帮助请下载,谢谢您的浏览!