1、嵌入式开发与应用实验指导书目 录实验一 HBE-EMPOSIII-SV210实验箱的构成 2实验二 Linux指令系统 11实验三 建立主机开发环境 18实验四 配置软件开发环境 19实验五 Bootloader编译与下载 29实验六 内核的编译与下载 48实验七 文件系统制作与烧写 54实验八 串口通讯实验 59实验九 网络应用编程 63实验一 HBE-EMPOSIII-SV210实验箱的构成1.1实验目的：了解三星S5PV210处理器的结构及特点；掌握HBE-EMPOSIII-SV210的系统构造及特征。1.2实验内容：对照实验箱，阅读并理解以下资料。阅读材料：1. HBE-EMPOSII
2、I-SV210 系统概要S5PV210 处理器构造及特征HBE-EMPOSIII-SV210基于采用ARM公司CortexTM-A8内核的三星S5PV210，是一种嵌入式教学用具。在了解HBE-EMPOSIII-SV210的系统结构之前，我们将对S5PV210做简要说明，并简单了解一下处理器的结构及特点。图 11 S5PV210 的框图S5PV210的框图如图1-1所示。从图中可知，S5PV210由ARM内核、系统外围设备（System Peripheral）、多媒体（Multimedia）、存储器接口（Memory Interface）、电源管理（Power Management）、连通性（
3、Connectivity）等功能块构成。S5PV210基于三星开发的ARM CortexTM -A8，是一种实现ARM架构V7-A的32位RISC微处理器。它为要求低耗电、高性能的移动及普通应用提供解决方案。此外，为提供3G和3.5G通信服务相关的优化硬件性能，S5PV210还具有64位内部总线结构。S5PV210针对动作视频处理（Motion Video Processing）、显示控制及缩放（Display Control And Scaling）等，内置了多个功能强大的硬件加速器。其中，MFC（Multi Format Codec，多格式编码译码器）提供了有关MPEG-1/2/4、H.2
4、63/H.264的编码和解码，还提供了有关VC1、Divx的解码。此外，这种硬件加速器还支持实时电视会议和模拟电视输出、HDMI接口。.S5PV210 的特征如下。 ARM CortexTM-A8 based CPU Subsystem with NEON 32/32KB I/D Cache, 512KB L2 Cache Operating frequency up to 800 Mhz at 1.1V, 1 GHz at 1.2V 64-bit Multi-layer bus architecture MSYS domain for ARM CortexTM-A8, 3D engine,
5、Multi Format Codec and Interrupt Controller Operating frequency up to 200 Mhz at 1.1V DSYS domain mainly for Display IPs(such as LCD controller, Camera interface, and TVout), and MDMA Operating frequency up to 166 Mhz at 1.1V PSYS domain mainly for other system component such as system peripherals,e
6、xternal memory interface, peri DMAs, connectivity IPs, and Audio interfaces. Operating frequency up to 133 Mhz at 1.1V Audio domain for low power audio play Advanced power management for mobile applications 64KB ROM for secure booting and 128KB RAM for security function 8-bit ITU 601/656 Camera Inte
7、rface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p30fps and coding of MPEG-2/VC1/Divx video up to 1080p30fps. JPEG codec support up to 80 Mpixels/s 3D Graphics Accele
8、ration with programmable shader up to 20M triangles/s and 1000 Mpixels/s 2D Graphics Acceleration up to 160MPixels/s 1/2/4/8 bpp Palletized or 8/16/24bpp Non-Palletized Color-TFT recommended up to XGA resolution. TV-out and HDMI interface support for NTSC and PAL mode with image enhancer MIPI-DSI an
9、d MIPI-CSI interface One AC-97 audio codec interface and 3-channel PCM serial audio interface 3-channel 24-bit I2S interface 1-channel TX only S/PDIF interface support for digital audio 3-channel I2C interface 2-channel SPI interface 4-channel UART including 3Mbps port for Bluetooth 2.0 On-chip USB
10、2.0 OTG supporting high speed (480Mbps, on-chip transceiver) On-chip USB 2.0 Host Asynchronous Modem Interface 4 SD/SDIO/HS-MMC interface. ATA/ATAPI-6 standard interface 24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA) 14x8 key matrix interface 10-chann
11、el 12-bit multiplexed ADC Configurable GPIOs Real time clock, PLL, timer with PWM and watch dog timer. System timer support for accurate tick time in power down mode(except sleep mode) Memory Subsystem Asynchronous SRAM/ROM/NOR Interface with x8 or x16 data bus. NAND Interface with x8 data bus Muxed
12、/Demuxed OneNAND Interface with x16 data bus. LPDDR1 Interface with x16 or x32 data bus (266400Mbps/pin DDR) DDR2 interface with x16 or x32 data bus (400Mbps/pin DDR) LPDDR2 interface (400Mbps/pin DDR)HBE-EMPOSIII-SV210的系统构造及特征在本节中，记述了目标板 HBE-EMPOSIII-SV210 的系统构造及特征。1.1.1 系统构造HBE-EMPOSIII-SV210以S5PV
13、210处理器为中心，主要由CPU模块（由NAND Flash memory、DDR2 SDRAM和缓存等构成）、通过NOR Flash Memory、LCD、UART、USB、Audio、Ethernet、Camera、SD Card slot等外围设备和FPGA控制的DipSwitch、DotMatrix、LEDs、CharacterLCD、OLED、7-Segment、蜂鸣器、Keypad、CMOS Camera等多种应用设备以及基板（提供通过Microcontroller控制的各种传感器）构成。下图 1-2 显示了 HBE-EMPOSIII-SV210 的整体框图。图 12 HBE-EM
14、POSIII-SV210 整体框图1.1.2 系统特征HBE-EMPOSIII-SV210主要由CPU模块和基板构成，将提供以下多种功能。. HBE-EMPOSIII-SV210 CPU Module 三星 S5PV210(ARM CortexTM-A8 Core) 512MByte DDR2 SDRAM : 128MByte * 4ea 256MByte NAND Flash Memory : 256MByte * 1ea HBE-EMPOSIII-SV210 Base Board(CPU Connected) 10/100Base-T Ethernet Controller 7”TFT L
15、CD with Touch Screen 3.1M Pixel CMOS Camera IIS Audio Codec : Speaker, MIC & Line-In USB 2.0 Host 3 Port and USB 2.0 OTG 1 Port RS232 Level UART 3 Port TTL Level UART 4 Port Bluetooth SD/MMC Card Connector 2 Port Composite Video Out 1 Port HDMI 1 Port SPDIF 1 Port 5 * 3 Keypad 1ea Jog Switch 1ea Pow
16、er On/Off Switch 2ea Boot Mode Switch HBE-EMPOSIII-SV210 Base Board(FPGA Connected) Character LCD(16 * 2) 1,3M Pixel CMOS Camera 6Digit 7-Segment 512Kbyte SRAM * 2ea 18,752 Logic Elements FPGA EP2C20 7 * 5 Dot Matrix 2ea 4 * 4 Keypad 8point DIP Switch 2ea OLED LED 8ea Buzzer Tact Switch 4ea Light Se
17、nsor Temperature/Humidity SensorHBE-EMPOSIII-SV210 产品构成下显示了一套HBE-EMPOSIII-SV210产品中所包含的所有组件。. HBE-EMPOSIII-SV210 产品构成项目FeatureHBE-EMPOSIII-SV210Byte BlasterUSB 线(Mini to A Type)LAN 线(Straight)LAN 线(Crossover)并行数据线Serial 线电源线教材及产品 CD实验设备：PC 机和HBE-EMPOSIII-SV210实验箱各一台；实验步骤：1、对照阅读材料，在实验箱上找到CPU模块、FPGA模块、
18、单片机模块；2、记录个模块主要的连接部件，主要的芯片型号；3、实验注意事项：本次实验无需打开实验箱电源。实验思考题：1、将下面材料翻译成中文，要求表达正确，专业术语表达恰当。（1）S5PV210 的特征如下。 ARM CortexTM-A8 based CPU Subsystem with NEON 32/32KB I/D Cache, 512KB L2 Cache Operating frequency up to 800 Mhz at 1.1V, 1 GHz at 1.2V 64-bit Multi-layer bus architecture MSYS domain for ARM Co
19、rtexTM-A8, 3D engine, Multi Format Codec and Interrupt Controller Operating frequency up to 200 Mhz at 1.1V DSYS domain mainly for Display IPs(such as LCD controller, Camera interface, and TVout), and MDMA Operating frequency up to 166 Mhz at 1.1V PSYS domain mainly for other system component such a
20、s system peripherals,external memory interface, peri DMAs, connectivity IPs, and Audio interfaces. Operating frequency up to 133 Mhz at 1.1V Audio domain for low power audio play Advanced power management for mobile applications 64KB ROM for secure booting and 128KB RAM for security function 8-bit I
21、TU 601/656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p30fps and coding of MPEG-2/VC1/Divx video up to 1080p30fps. JPEG codec support up to 80 Mpixel
22、s/s 3D Graphics Acceleration with programmable shader up to 20M triangles/s and 1000 Mpixels/s 2D Graphics Acceleration up to 160MPixels/s 1/2/4/8 bpp Palletized or 8/16/24bpp Non-Palletized Color-TFT recommended up to XGA resolution. TV-out and HDMI interface support for NTSC and PAL mode with imag
23、e enhancer MIPI-DSI and MIPI-CSI interface One AC-97 audio codec interface and 3-channel PCM serial audio interface 3-channel 24-bit I2S interface 1-channel TX only S/PDIF interface support for digital audio 3-channel I2C interface 2-channel SPI interface 4-channel UART including 3Mbps port for Blue
24、tooth 2.0 On-chip USB 2.0 OTG supporting high speed (480Mbps, on-chip transceiver) On-chip USB 2.0 Host Asynchronous Modem Interface 4 SD/SDIO/HS-MMC interface. ATA/ATAPI-6 standard interface 24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA) 14x8 key mat
25、rix interface 10-channel 12-bit multiplexed ADC Configurable GPIOs Real time clock, PLL, timer with PWM and watch dog timer. System timer support for accurate tick time in power down mode(except sleep mode) Memory Subsystem Asynchronous SRAM/ROM/NOR Interface with x8 or x16 data bus. NAND Interface
26、with x8 data bus Muxed/Demuxed OneNAND Interface with x16 data bus. LPDDR1 Interface with x16 or x32 data bus (266400Mbps/pin DDR) DDR2 interface with x16 or x32 data bus (400Mbps/pin DDR) LPDDR2 interface (400Mbps/pin DDR)（2）系统特征 HBE-EMPOSIII-SV210 CPU Module 三星 S5PV210(ARM CortexTM-A8 Core) 512MBy
27、te DDR2 SDRAM : 128MByte * 4ea 256MByte NAND Flash Memory : 256MByte * 1ea HBE-EMPOSIII-SV210 Base Board(CPU Connected) 10/100Base-T Ethernet Controller 7”TFT LCD with Touch Screen 3.1M Pixel CMOS Camera IIS Audio Codec : Speaker, MIC & Line-In USB 2.0 Host 3 Port and USB 2.0 OTG 1 Port RS232 Level
28、UART 3 Port TTL Level UART 4 Port Bluetooth SD/MMC Card Connector 2 Port Composite Video Out 1 Port HDMI 1 Port SPDIF 1 Port 5 * 3 Keypad 1ea Jog Switch 1ea Power On/Off Switch 2ea Boot Mode Switch HBE-EMPOSIII-SV210 Base Board(FPGA Connected) Character LCD(16 * 2) 1,3M Pixel CMOS Camera 6Digit 7-Se
29、gment 512Kbyte SRAM * 2ea 18,752 Logic Elements FPGA EP2C20 7 * 5 Dot Matrix 2ea 4 * 4 Keypad 8point DIP Switch 2ea OLED LED 8ea Buzzer Tact Switch 4ea Light Sensor Temperature/Humidity Sensor2、写出实验中记录的各模块主要的连接部件及主要的芯片型号，并简单描述各芯片的功能。实验二 Linux指令系统2.1实验目的：熟悉Linux常用的指令；2.2实验设备及软件环境：PC 机一台；操作系统：Ubuntu 8
30、.04；（一）目录操作实验内容：1) 查看/tmp目录下的内容；2) 如果/tmp目录下没有子目录myshare，就建立该目录；3) 要求目录myshare的拥有者为bin，工作组为bin；4) 要求myshare下的所有文件和子目录都自动拥有工作组为bin。实验配置文件及命令： 1配置文件：无2命令：/bin/ls，/bin/mkdir，/bin/chown，/bin/chmod，/bin/chgrp 实验步骤：1当前的分区表信息。rootlinux /# cd /tmprootlinux tmp# lsksocket-root linux-2.6.11.1 orbit-root proftpd-1.2.9 proftpd-1.2.9.tar.gz2目录myshare。rootlinux tmp# mkdir mysharerootlinux tmp# ls -ld myshare/drwxr-xr-x 2 root root 4096 May 27 14:01 myshare/3修改目录的拥有者和工作组。rootlinux tmp# chown bin myshare/rootlinux tmp# ls -ld myshare/drwxr-xr-x 2 bin
