1、local control and data acquisition CDAQ subsystem for gammaray276Land information system: An interoperable framework for high resolution land surface modelingOriginal Research ArticleEnvironmental Modelling & Software, Volume 21, Issue 10, October 2006, Pages 1402-1415S.V. Kumar, C.D. Peters-Lidard,
2、 Y. Tian, P.R. Houser, J. Geiger, S. Olden, L. Lighty, J.L. Eastman, B. Doty, P. Dirmeyer, J. Adams, K. Mitchell, E.F. Wood, J. SheffieldClose preview| Related articles|Related reference work articles AbstractAbstract | Figures/TablesFigures/Tables | ReferencesReferences AbstractKnowledge of land su
3、rface water, energy, and carbon conditions are of critical importance due to their impact on many real world applications such as agricultural production, water resource management, and flood, weather, and climate prediction. Land Information System (LIS) is a software framework that integrates the
4、use of satellite and ground-based observational data along with advanced land surface models and computing tools to accurately characterize land surface states and fluxes. LIS employs the use of scalable, high performance computing and data management technologies to deal with the computational chal
5、lenges of high resolution land surface modeling. To make the LIS products transparently available to the end users, LIS includes a number of highly interactive visualization components as well. The LIS components are designed using object-oriented principles, with flexible, adaptable interfaces and
6、modular structures for rapid prototyping and development. In addition, the interoperable features in LIS enable the definition, intercomparison, and validation of land surface modeling standards and the reuse of a high quality land surface modeling and computing system.Article Outline1. Introduction
7、2. Land surface modeling in LIS3. Components of LIS4. Interoperability in LIS 4.1. Interoperable design features in LIS4.2. Adopted interoperable features in LIS5. Results6. Summary and future directionsAcknowledgementsReferencesPurchase$ 19.95277Wide-range, fast and robust estimation of power syste
8、m frequencyOriginal Research ArticleElectric Power Systems Research, Volume 65, Issue 2, May 2003, Pages 109-117M. Karimi-Ghartemani, M. R. IravaniClose preview| Related articles|Related reference work articles AbstractAbstract | Figures/TablesFigures/Tables | ReferencesReferences AbstractA novel me
9、thod of frequency estimation, for power system applications such as control and protection, is proposed and its performance is evaluated. The proposed frequency estimator can measure small as well as large deviations from the nominal point. It closely follows step, ramp and oscillatory variations of
10、 the frequency over time. Other significant features of the proposed algorithm are: (a) structural simplicity, which renders it suitable for hardware/software implementation; (b) performance robustness in the presence of DC offset and harmonic components; (c) noise immunity; (d) performance robustne
11、ss with respect to external disturbances such as commutation notches and switching transients; and (e) flexibility of control over speed and accuracy. Rate of change of frequency is also directly provided by the estimator which is a requirement in some system protection algorithms. In a highly pollu
12、ted environment, the proposed estimator can be set to measure the frequency in few cycles of the signal and with a steady-state error which is limited to 0.02 Hz.Article Outline1. Introduction2. Problem definition3. Overview of the EPLL4. Proposed power frequency estimator5. Study results 5.1. Pure
13、sinusoidal5.2. Presence of DC offset5.3. Presence of harmonics5.4. Presence of noise5.5. Effect of disturbances5.6. Effect of misadjustment of internal parameters5.7. Compound effect of undesired components5.8. Step change in the frequency5.9. Oscillatory frequency variation5.10. Oscillating ramp fr
14、equency5.11. Impulsive disturbances5.12. Rate of change of frequency6. Summary and conclusionsReferencesPurchase$ 41.95278A tunable high-performance architecture for enhancement of stream video captured under non-uniform lighting conditionsOriginal Research ArticleMicroprocessors and Microsystems, V
15、olume 32, Issue 7, October 2008, Pages 386-393Ming Z. Zhang, Ming-Jung Seow, Li Tao, Vijayan K. AsariClose preview| Related articles|Related reference work articles AbstractAbstract | Figures/TablesFigures/Tables | ReferencesReferences AbstractA novel architecture for performing hue-saturation-value
16、 (HSV) domain enhancement of digital color images captured under non-uniform lighting conditions is proposed in this paper for video streaming applications. The approach promotes log-domain computation to eliminate all multiplications, divisions and exponentiations utilizing the compact high-speed l
17、ogarithmic estimation modules. An optimized quadrant symmetric architecture is incorporated into the design of homomorphic filter for the enhancement of intensity value. Efficient modules are also presented for conversion between RGB and HSV color spaces with tunable H and S components in HSV for mo
18、re flexible color rendering. The design is able to bring out details hidden in shadow regions of the image and preserve the bright parts with adjustable vividness and color shift for improvement of visual quality while maintaining its consistency. It is capable of producing 187.86 million outputs pe
19、r second (MOPs) on Xilinxs Virtex II XC2V2000-4ff896 field programmable gate array (FPGA) at a clock frequency of 187.86MHz. It can process over 179.1 (10241024) frames per second, which is very suitable for high definition videos, and consumes approximately 70.7% and 76.8% less hardware resource wi
20、th 127% and 280% performance boost when compared to the designs with machine learning algorithm in M.Z. Zhang, M.J. Seow, V.K. Asari, A high performance architecture for color image enhancement using a machine learning approach, International Journal of Computational Intelligence Research Special Is
21、sue on Advances in Neural Networks 2(1) (2006) 4047, and with separated dynamic and contrast enhancements in H.T. Ngo, M.Z. Zhang, L. Tao, V.K. Asari, Design of a high performance architecture for real-time enhancement of video stream captured in extremely low lighting environment, International Jou
22、rnal of Embedded Systems: Special Issue on Media and Stream Processing, in press, respectively. This approach also provide 83.4 times performance gain with more consistent fidelity in the results compared to some DSP based implementations (256256 frame size) G.D. Hines, Z. Rahman, D.J. Jobson, G.A.
23、Woodell, DSP implementation of the retinex image enhancement algorithm, visual information processing XIII, in: Proceedings of the SPIE, vol. 5438, 2004, pp. 1324; G.D. Hines, Z. Rahman, D.J. Jobson, G.A. Woodell, Single-scale retinex using digital signal processors, in: Proceedings of the Global Si
24、gnal Processing Conference, September 2004, pp. 16 under the reflectance-illuminance category of image enhancement models.Article Outline1. Introduction2. Related works 2.1. Quadrant symmetry property2.2. Log-domain computation3. Reflectance-illuminance model 3.1. Homomorphic based HSV-domain enhanc
25、ement3.2. Brief comparison of algorithms under the model4. Design of system architecture 4.1. Overview4.2. Architecture of homomorphic filter unit 4.2.1. Architecture of pipelined processing elements in homomorphic filter4.3. Data buffer unit4.4. Architecture for RGB2HSV color space conversion4.5. A
26、rchitecture for HSV2RGB color space conversion5. Hardware simulation and error analysis6. Resource utilization and performance evaluation7. ConclusionReferencesPurchase$ 35.95279A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systemsOriginal Research ArticleParallel
27、 Computing, Volume 36, Issues 10-11, October-November 2010, Pages 572-590Jos L. Risco-Martn, David Atienza, J. Manuel Colmenar, Oscar GarnicaClose preview| Related articles|Related reference work articles AbstractAbstract | Figures/TablesFigures/Tables | ReferencesReferences AbstractFor the last 30
28、years, several dynamic memory managers (DMMs) have been proposed. Such DMMs include first fit, best fit, segregated fit and buddy systems. Since the performance, memory usage and energy consumption of each DMM differs, software engineers often face difficult choices in selecting the most suitable ap
29、proach for their applications. This issue has special impact in the field of portable consumer embedded systems, that must execute a limited amount of multimedia applications (e.g., 3D games, video players, signal processing software, etc.), demanding high performance and extensive memory usage at a
30、 low energy consumption. Recently, we have developed a novel methodology based on genetic programming to automatically design custom DMMs, optimizing performance, memory usage and energy consumption. However, although this process is automatic and faster than state-of-the-art optimizations, it deman
31、ds intensive computation, resulting in a time-consuming process. Thus, parallel processing can be very useful to enable to explore more solutions spending the same time, as well as to implement new algorithms. In this paper we present a novel parallel evolutionary algorithm for DMMs optimization in
32、embedded systems, based on the Discrete Event Specification (DEVS) formalism over a Service Oriented Architecture (SOA) framework. Parallelism significantly improves the performance of the sequential exploration algorithm. On the one hand, when the number of generations are the same in both approaches, our parallel optimization framework is able to
