1、外文翻译微处理器报告附录A科技文章摘译MICROPROCESSOR REPORTAtmel AVR Brings RISC to 8-Bit WorldBetter Performance Than Other 8-Bit Chips With Same Low CostBy Jim TurleyProving the adage that all technologies eventually filter down into commodity products, Atmel has brought RISC design philosophy to 8-bit micro-control
2、lers. Dubbed AVR, this new architecture provides all the usual benefits of RISC: faster clock rates, better performance, and more efficient compiler optimization. Atmel also promises better code density and lower cost than comparable 8-bit micro-controllers.AVR competes with several well-established
3、 micro-controller dynasties such as the 6805, 68HC11, and 8051.Competition also comes from Microchips PIC family, a more modern design thats expanded rapidly in the past few years. Atmel hopes AVR will appeal to embedded designers who are willing to tackle a new architecture to get more performance
4、than the entrenched micro-controller families can provide.AVR is the first in-house CPU design from Atmel, a billion-dollar company better known for its flash memory and E2PROM products. The company also sells a dozen flash-based derivatives of the popular 8051family, which it produces under license
5、 from Intel.Design Melds RISC and Micro-controller IdeasThe CPU resembles most RISC processors but has smaller registers. It was originally developed by a pair of researchers in Trondheim,Norway, before their consultancy was acquired by Atmel in 1995. Core CPU development still takes place in Norway
6、, while memory and peripheral development is centered in Atmels San Jose (Calif.) facility. The core features 32 identical 8-bit registers, as Figure 1 shows. Any register can hold addresses or data. Since 8-bit address pointers are fairly worthless even in an 8-bit device, the last six registers ca
7、n be used in pairs, as address pointers. Dubbed X, Y, and Z, these three meta-registers can be used for any load or store operation. The pointers can be post incremented or predecremented at the programmers option. Finally, a 6-bit displacement can be added to the contents of the pointer, a useful o
8、ption for addressing array elements. This mode is not available for the X pointer; that op code is reserved for the LDI (load immediate constant) instruction.Figure 1. Unlike other 8-bit controllers, AVR has a set of 32 8-bit registers. The last six registers can be paired to form three address poin
9、ters.As with many low-end micro-controllers, the register file is mapped into the address space, and vice versa. The first 32 bytes of memory, 0x000x1F, correspond to registers R0R31. The chips status registerwhich contains the overflow, carry, sign, and other flagsas well as other “internal” regist
10、ers are also memory mapped. This allows any register to be manipulated using standard memory references instead of special control-register instructions. For all intents and purposes, the CPU has no pipeline. It retrieves both source operands, executes the instruction, and stores the result in a sin
11、gle clock cycle. Branch latency is one clock for taken branches. All operations are register-to-register; the chip follows a strict load/store model. The great majority of AVR instructions are 16 bits long. Only four 32-bit instructions exist, allowing limited use of absolute 16-bit addressing. AVR
12、separates the program and data spaces; although data pointers can be 16 bits, the PC (program counter) is only 12 bits wide, for 8K of code space.Instruction Set As Regular As PossibleThe compact instruction set necessarily forces some compromises, the first of which affects immediate values (litera
13、ls). Very few instructions accept immediate values, and those that do (ADIW, SUBI, ORI, etc.) work only on the upper half (R16R31) of the register set, as Table 1 shows. Even after shaving a bit from the operand-specified field, these instructions sometimes have room for only 6-bit immediate values.
14、 Table 1. Atmels AVR 8-bit RISC instruction set follows a strict load/store model, with a few simple indirect addressing modes, including post increment and preferment. The architecture also includes a number of individual bit-manipulation instructions.The ADIW and SBIW instructions (add/subtract im
15、mediate from word) are even more restrictive, operating on only the last eight registers, R24R31. These instructions are meant primarily to add small offsets (063 bytes) to the X, Y, and Z pointers. There is a wealth of conditional branch instructions: namely, two for each of the eight flags in the
16、status register. With little 7-bit offsets, these instructions can deflect execution only 64 instructions in either direction. For bigger displacements, RJMP can shift code by 2K, which is usually plenty, given the chips small code space. AVR also has a collection of interesting “skip” operations (S
17、BRC, SBRS, SBIC, and SBIS) that skip over the next instruction if any bit in any register is set or clear. If the skipped instruction is a long-displacement jump, these skips can be used to effectively create conditional long-displacement branches. Alternatively, they can be used to skip a single ar
18、ithmetic or logical operation in a string of operations, creating conditional operations somewhat similar to ARMs. None of the AVR chips has a native multiply operationmuch less a dividealthough one has been defined. As defined, MUL multiplies any two 8-bit registers and deposits the 16-bit result i
19、n R0 and R1.When implemented, MUL executes in just two clock cycles, which is five times faster than the 68HC11s 10 clocks; even Motorolas newer 68HC12 (see MPR 5/27/96, p. 1) needs 3 clocks. Atmel expects to deploy its multiplier in future AVR chips as clock speeds increase and the chips take on si
20、mple signal-processing tasks. Instructions Are Rich in Bit ManipulationAs with most micro-controllers, the AVR family has a host of bit-twiddling options, including 16 explicit instructions to set and clear every flag in its status register. This seems like a lopsided use of op code space; the same
21、result could have been achieved with normal logical operations. For deeply embedded applications, however, this was probably the right choice. Masking operations use precious address pointers and one or more registers; the SEx/CLx instructions use neither. The chip can also set or clear any bit in a
22、ny general purpose or I/O register; SER and CLR wipe the contents of an entire register at once. SBR and CBR, which set or clear multiple bits at a time, are aliases for ORI and ANDI, respectively. Initial Launch Includes Five PartsAtmel launched its AVR product line with four basic chips: the 90S12
23、00, the 2313, the 4414, and the 8515. The latter three devices are very similar, differing mainly in the amount of memory on the chip: 2K, 4K, or 8K of flash, with the amount of on-chip SRAM and E2PROM also increasing. The runt of the litter, the 1200, has only 1K of flash memory, no SRAM, no periph
24、erals, and a restricted instruction set. With neither SRAM nor an external bus, the 1200 must use on-chip flash for data storage, which will slow execution considerably unless programmers can get by with juggling the register set alone. The 1200 are also the only chip in the family currently in prod
25、uction. In 1,000-unit quantities, the 20-pin 90S1200 sells for a paltry $1.65. Its not often that the number of data bits outnumbers the pins on the package, but Atmel managed to get close with its 1220 device, an 8-pin version of the 1200. After power, ground, and crystal connections, only four pin
26、s are free for I/O. Most AVR chips come in 20-pin DIP or SOIC packages, which provide access to more I/O lines; only in a 40-pin package do the chips bond out their address and data buses for access to external memory. All the parts are fabricated on Atmels four 0.8-micron two-layer-metal fab lines
27、in Colorado Springs and Rousset (France). This is the same memory process Atmel uses for its E2PROM and flash devices, and for its 8051 chips with integrated flash. The 1200 measure about 24mm2 overall, and as the die photo in Figure 2 shows, the chip is nearly all logic. Memory processes typically
28、dont produce very compact (or fast) logic, but most AVR chips will be dominated by memory and peripherals, and clock speeds arent very high. Figure 2. The 90S1200 measures about 4.3 5.5 mm in Atmels 0.8-micron two-layer-metal flash-memory process. For Once, RISC Techniques Improve Code DensityIts so
29、metimes hard to get excited about 8-bit processors, yet Atmels AVR design is as different from others in its class as the first RISC machine was from big systems more than a decade ago. With its large register file and orthogonal instruction set, AVR is far more modern than its competitors. Atmels n
30、ew CPU will be particularly appealing to programmers moving down the microprocessor food chain from 32-bit or 16-bit chips and who are accustomed to flexible register sets. For programmers moving up from, say, the 8051, AVR will be a real eye-opener. For example, the 8051, 6805, and PIC all make do
31、with a single accumulator; the68HC11 and HC12 have just two. This makes AVR easier to program at the assembly level and easier to optimize with a compiler. The big register set reduces dependence on memory, which improves speed and shrinks data-storage requirements. Counterintuitively, AVRs RISC-lik
32、e instruction set also helps improve its code density over that of other 8-bitters, according to Atmel. Its CPI (compare immediate) instruction avoids the relatively awkward construct of loading, subtracting, and checking flags used on the 6805 and PIC. Adding two numbers on the 8051, 6805, or PIC usually involves shuffling both operands through the accumulator and storing the result; AVR simply adds two registers with one instruction in one cycle. AVR is not pure RISC-some instructions are longer than othersnor is it the first 8-bit micro-controller with a big register file
