1、汽车尾灯控制电路设计正文1 引言在日新月异的21世纪里，电子产品得到了迅速发展。许多电器设备都趋于人性化、智能化，这些电器设备大部分都含有CPU控制器或者是单片机。单片机以其高可靠性、高性价比、低电压、低功耗等一系列优点，近几年得到迅猛发展和大范围推广，广泛应用于工业控制系统、通讯设备、日常消费类产品和玩具等。并且已经深入到工业生产的各个环节以及人民生活的各个方面，如车间流水线控制、自动化系统等、智能型家用电器（冰箱、空调、彩电）等。用单片机来控制的小型电器产品具有便携实用，操作简单的特点。本文设计的汽车尾灯控制电路属于小型智能电子产品。利用单片机进行控制，实时时钟芯片进行记时，外加掉电存储电
2、路和显示电路。此设计具有相当重要的现实意义和实用价值。2 系统概述本设计以AT89S52单片机为核心，构成单片机控制电路，完成对它们的自动调整和掉电保护。人机接口由四个按键来实现，用这四个按键对汽车左转，右转，停车和检测进行控制。软件控制程序实现所有的功能。整机电路使用+5V稳压电源，可稳定工作。系统框图如图2-1所示，其软硬件设计简单，可广泛应用于长时间工作的系统中。图2-1 系统框图3 方案选择 由于汽车尾灯控制电路的种类比较多，因此方案选择在设计中是至关重要的。正确地选择方案可以减小开发难度，缩短开发周期，降低成本，更快地将产品推向市场。3.1 方案1基于AT89S52单片机的汽车尾灯控
3、制电路设计直接用AT89S52单片机来实现汽车尾灯控制电路设计。AT89S52是一种带8K字节闪烁可编程可擦除只读存储器的低电压，高性能CMOS 8位微处理器，俗称单片机。单片机的可擦除只读存储器可以反复擦写1000余次。由于将多功能8位CPU和闪烁存储器组合在单个芯片中，ATMEL的AT89S52是一种高效微控制器，为很多嵌入式控制系统提供了一种灵活性高且价廉的方案。用单片机来实现汽车尾灯控制电路设计，无须外接其他芯片，充分利用了单片机的资源。3.2 方案2基于电子元件的汽车尾灯控制电路设计 用电子元件接的汽车尾灯控制电路，电路复杂，接点较多，电路稳定性差。 汽车左右和刹车仿真电路汽车尾灯控
4、制电路设计总体框图4 系统硬件电路的设计按照系统设计功能的要求，初步确定设计系统由主控模块、键盘接口模块、显示模块共3个模块组成，电路系统构成框图如图4-1所示。主控芯片使用52系列AT89S52单片机，图4-1 汽车尾灯控制电路系统构成框图4.1 系统核心部分闪电存储型器件AT89S524.1.1 AT89S52具有下列主要性能5： 8KB可改编程序Flash存储器（可经受1000次的写入/擦除周期） 全静态工作：0Hz24MHz三级程序存储器保密1288字节内部RAM32条可编程I/O线2个16位定时器/计数器6个中断源可编程串行通道片内时钟振荡器4.1.2 AT89S52的引脚及功能AT
5、89S52单片机的管脚说明如图4-2所示。图4-2 AT89S52的管脚(1) 主要电源引脚 VCC 电源端 GND 接地端(2) 外接晶体引脚XTAL1和XTAL2 XTAL1 接外部晶体的一个引脚。在单片机内部，它是构成片内振荡器的反相放大器的输入端。当采用外部振荡器时，该引脚接收振荡器的信号，既把此信号直接接到内部时钟发生器的输入端。 XTAL2 接外部晶体的另一个引脚。在单片机内部，它是上述振荡器的反相放大器的输出端。采用外部振荡器时，此引脚应悬浮不连接。(3) 控制或与其它电源复用引脚RST、ALE/PROG、/PSEN和/EA/VPP RST 复位输入端。 当振荡器运行时，在该引脚
6、上出现两个机器周期的高电平将使单片机复位。 ALE/PROG 当访问外部存储器时，ALE（地址锁存允许）的输出用于锁存地址的低位字节。即使不访问外部存储器，ALE端仍以不变的频率（此频率为振荡器频率的1/6）周期性地出现正脉冲信号。因此，它可用作对外输出的时钟，或用于定时目的。然而要注意的是：每当访问外部数据存储器时，将跳过一个ALE脉冲。在对Flash存储器编程期间，该引脚还用于输入编程脉冲（/PROG）6。 /PSEN 程序存储允许（/PSEN）输出是外部程序存储器的读选通信号。当AT89S52/LV52由外部程序存储器取指令（或常数）时，每个机器周期两次/PSEN有效（既输出2个脉冲）。
7、但在此期间内，每当访问外部数据存储器时，这两次有效的/PSEN信号将不出现。/EA/VPP 外部访问允许端。要使CPU只访问外部程序存储器（地址为0000HFFFFH），则/EA端必须保持低电平（接到GND端）。当/EA端保持高电平（接VSS端）时，CPU则执行内部程序存储器中的程序。(4) 输入/输出引脚 P0.0 P0.7、P1.0P1.7、P2.0 P2.7 和P3.0P3.7P0端口（P0.0 P0.7） P0是一个8位漏极开路型双向I/O端口。作为输出口用时，每位能以吸收电流的方式驱动8个TTL输入，对端口写1时，又可作高阻抗输入端用。P1端口（P1.0 P1.7） P1是一个带有内
8、部上拉电阻的8位双向I/O端口。P1的输出缓冲器可驱动（吸收或输出电流方式）4个TTL输入。对端口写1时，通过内部的上拉电阻把端口拉到高电位，这时可用作输入口。作输入口时，因为有内部的上拉电阻，那些被外部信号拉低的引脚会输出一个电流。 P2端口 （P2.0P2.7） P2是一个带有内部上拉电阻的8位双向I/O端口。P2的输出缓冲器可驱动（吸收或输出电流方式）4个TTL输入。对端口写1时，通过内部的上拉电阻把端口拉到高电位，这时可用作输入口。P2作输入口使用时，因为有内部的上拉电阻，那些被外部信号拉低的引脚会输出一个电流。P3端口（P3.0P3.7） P3口管脚是8个带内部上拉电阻的双向I/O口
9、，可接收输出4个TTL门电流。当P3口写入“1”后，它们被内部上拉为高电平，并用作输入。作为输入，由于外部下拉为低电平，P3口将输出电流，这是由于上拉的缘故。P3口也可作为AT89S52的一些特殊功能，这些特殊功能见表4-17。表4-1 P3端口的特殊功能 端口引脚 兼 用 功 能 P3.0RXD （串行输入口） P3.1TXD （串行输出口） P3.2/INT0 （外部中断0） P3.3/INT1 （外部中断1） P3.4T0 （ 定时器0的外部输入） P3.5T1 （定时器1的外部输入） P3.6/WR （外部数据存储器写选通） P3.7/RD （外部数据存储器读选通）4.5 键盘电路本设
10、计共采用按键4个，分别与单片机的P2.0、P2.1、P2.2、P2.3口相连，分别对应汽车左转，汽车右转，刹车和检测的功能。7 结论本设计硬件电路较简单，所用器件较少，电路中使用了AT89S52单片主要芯片,实现了预计功能。在对芯片的管脚功能和用法有充分的了解后，根据设计要求设计硬件电路，然后通过软件编程，用按键进行控制，用发光二极管进行显示。汽车尾灯控制电路可以正常显示汽车的左转，右转，停车和检测功能，基本完成了预期要实现的目标。参考文献1康华光主编，电子技术基础(数字部分)，高等教育出版社2标准集成电路数据手册TTL电路，电子工业出版社致 谢不知不觉，六周的毕业设计结束了。我的毕业论文已整
11、理完毕，电路调试进展良好。毕业设计的完成意味着我的大学学习生活即将结束，从此我将进入一个新的人生旅途、开始一段崭新的生活工作。在此，我衷心地感谢所有在我做毕业设计期间帮助过我的人。 首先我要感谢我的指导老师李杰的大力帮助和支持。在整个设计过程当中，李老师在大局上指导我毕业设计的每一进程，还在百忙中抽空为我答疑解难，帮我分析讲解毕业设计中所遇到的问题。不仅如此，李老师还无私的给我提供了丰富的学习资源和良好的学习环境，为我的毕业设计带来了很大方便。同时在我完成毕业设计的过程中提供了很多指导性的意见，使我受益匪浅。另外，李老师渊博的学识、严谨的治学态度和为人给了我很大的教育，这些将使我终身受益。在此
12、，我衷心感谢李老师给予我的帮助和教育。此外，我还要感谢夏九和李国华同学给予我的无私的帮助，他们在程序编写和调试过程中给予了我莫大的帮助。在此，我真诚地感谢他们。最后，我要感谢我的母校天津工程师范学院，在校期间，这里给我留下了美好的回忆。特别是在我即将踏上工作岗位的同时，毕业设计整个过程给了我这样一个锻炼的机会，使我加深了对以前知识的理解和巩固，拓宽了知识面，也提高了我对所学知识的综合应用能力。我要对母校说：母校有我三五载，我爱母校一万年。祝愿母校的将来更美好！附录1：汽车尾灯控制电路设计电路原理图附录2 主程序 org 00h ajmp start ORG 001BH ;定时器T1中断程序入口
13、 LJMP time1 ;跳至INTT1执行 org 0030hstart: mov TMOD,#10h mov IE,#88h MOV TH1,#00h MOV TL1,#00h mov r7,#03h; setb TR1turn: jnb p2.0,is_key jnb p2.1,is_key jnb p2.2,is_key jnb p2.3,is_key orl p1,#0ffh;is_key : jb p2.3,no_check; anl p1,#0c0h; jmp turnno_check: jmp turntime1: push acc mov TH1,#010h mov TL1,
14、#00h jb p2.0,left djnz r7,return mov r7,#3 xrl p1,#3fhleft: jb p2.1,right dec r7; cjne r7,#6,next1; mov p1,#0fbhnext1: cjne r7,#3,next2; mov p1,#0fdh;next2: cjne r7,#0,right; mov p1,#0feh mov r7,#9;right: jb p2.2,return dec r7; cjne r7,#6,next11; mov p1,#0f7hnext11: cjne r7,#3,next21; mov p1,#0efh;n
15、ext21: cjne r7,#0,return; mov p1,#0dfh mov r7,#9;return: pop acc reti end英文资料及中文翻译6 TRANSMISSIONS OF DIGITAL DATA: INTERFACES AND MODEMS(From Introduction to Data Communications and Net Working, Behrouz Forouzan)Once we have encoder our information into a format that can be transmitted, the next ste
16、p is to investigate the transmission process itself. Information-processing equipment such as PCs generate encoded signals but ordinarily require assistance to transmit those signals over a communication link. For example, a PC generates a digital signal but needs an additional device to modulate a
17、carrier frequency before it is sent over a telephone line. How do we relay encoded data from the generating device to the next device in the process? The answer is a bundle of wires, a sort of mini communication link, called an interface.Because an interface links two devices not necessarily made by
18、 the same manufacturer, its characteristics must be defined and standards must be established. Characteristics of an interface include its mechanical specifications (how many wires are used to transport the signal); its electrical specifications (the frequency, amplitude, and phase of the expected s
19、ignal); and its functional specifications (if multiple wires are used, what does each one do?). These characteristics are all described by several popular standards and are incorporated in the physical layer of the OSI model.6.1 DIGITAL DATA TRANSMISSIONOf primary concern when considering the transm
20、ission of data from one device to another is the wiring. And of primary concern when considering the wiring is the data stream. Do we send one bit at a time, or do we group bits into larger groups and, if so, how? The transmission of binary data across a link can be accomplished either in parallel m
21、ode or serial mode. In parallel mode, multiple bits are sent with each clock pulse. In serial mode, one bit is sent with each clock pulse. While there is only one way to send parallel data, there are two subclasses of serial transmission: synchronous and asynchronous (see Figure 6-1).Parallel Transm
22、issionBinary data, consisting of 1s and 0s, may be organized into groups of n bits each. Computers produce and consume data in groups of bits much as we conceive of and use spoken language in the form of words rather than letters. By grouping, we can send data n bits at a time instead of one. This i
23、s called parallel transmission. Figure 6-1Data transmission The mechanism for parallel transmission is a conceptually simple one: use n wires to send n bits at one time. That way each bit has its own wire, and all n bits of one group can be transmitted with each clock pulse from one device to anothe
24、r. Figure 6-2 shows how parallel transmission works for n=8.Typically the eight wires are bundled in a cable with a connector at each end. Figure 6-2Parallel transmissionThe advantage of parallel transmission is speed. All else being equal, parallel transmission can increase the transfer speed by a
25、factor of n over serial transmission. But there is a significant disadvantage: cost. Parallel transmission requires n communication lines (wires in the example) just to transmit the data stream. Because this is expensive, parallel transmission is usually limited to short distances, up to a maximum o
26、f say 25 feet.Serial TransmissionIn serial transmission one bit follows another, so we need only one communication channel rather than n to transmit data between two communicating devices .The advantage of serial over parallel transmission is that with only one communication channel, serial transmis
27、sion reduces the cost of transmission over parallel by roughly a factor of n.Since communication within devices is parallel, conversion devices are required at the interface between the sender and the line (parallel-to-parallel).Serial transmission occurs in one of two ways: asynchronous or synchron
28、ous.Asynchronous TransmissionAsynchronous transmission is so named because the timing of a signal is unimportant. Instead, information is received and translated by agreed-upon patterns. As long as those patterns are followed, the receiving device can retrieve the information without regard to the r
29、hythm in which it is sent. Patterns are based on grouping the bit stream into bytes. Each group, usually eight bits, is sent along the link as a unit. The sending system handles each group independently, relaying it to the link whenever ready, without regard to a timer. Without a synchronizing pulse
30、, the receiver cannot use timing to predict when the next group will arrive. To alert the receiver to the arrival of a new group, therefore, an extra bit is added to the beginning of each byte. This bit, usually a 0, is called the start bit. To let the receiver know that the byte is finished, one or
31、 more additional bits are appended to the end of the byte. These bits, usually 1s, are called stop bits. By this method, each byte is increased in size to at least 10 bits, of which 8 are information and 2 or more are signals to the receiver. In addition, the transmission of each byte may then be followed by a gap of varying duration. This gap can be represented either by an idle channel or by a stream of additional stop bits.In asynchronous transmission we send one start bit (0) at the beginning and one or more stop bits (1s) at the end of each byte.
