1、基于VHDL语言的EDA实验报告附源码EDA 实 验 报 告多功能电子钟姓名: 张 红 义班级： 10级电科五班学号： 1008101143指导老师：贾树恒电子钟包括：主控模块，计时模块，闹钟模块，辅控模块，显示模块，蜂鸣器模块，分频器模块。1主控模块：主要功能：控制整个系统，输出现在的状态，以及按键信息。源代码:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity mc isport(functionswitch,k,set,li
2、ghtkey: in std_logic;chose21,setout: out std_logic;lightswitch:buffer std_logic;modeout,kmodeout : out std_logic_vector(1 downto 0);setcs,setcm,setch,setas,setam,setah:out std_logic);end mc;architecture work of mc issignal mode,kmode:std_logic_vector(1 downto 0);signal light,chose21buf:std_logic;sig
3、nal setcount:std_logic_vector(5 downto 0);beginprocess(functionswitch,k,set,lightkey)beginif functionswitchevent and functionswitch=1 thenmode=mode+1;end if;if lightkeyevent and lightkey=1 thenlightswitch=not lightswitch;end if;if mode=01 then chose21buf=0;else chose21buf=1;end if;if kevent and k=1
4、thenif mode=01 or mode=11 thenkmode=kmode+1;end if; end if;if set=1 thenif mode = 01 thenif kmode=01 then setcount=000001;elsif kmode=10 then setcount=000010;elsif kmode=11 thensetcount=000100;else setcount=000000;end if;elsif mode = 11 then if kmode=01 then setcount=001000;elsif kmode=10 thensetcou
5、nt=010000;elsif kmode=11 then setcount=100000;else setcount=000000;end if; end if; end if;if set=0 then setcount=00000”;end if; setout=set;modeout=mode;kmodeout=kmode;chose21=chose21buf;setcs=setcount(0);setcm=setcount(1);setch=setcount(2);setas=setcount(3);setam=setcount(4);setah=setcount(5);end pr
6、ocess; end work;仿真波形：2. 计时模块主要功能：记录时间，正常计时。60进制library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity count60 is port( clk ,clr :in std_logic; co : out std_logic; outh :out std_logic_vector(7 downto 4); outl :out std_logic_vector(3 downto 0); en
7、d count60 ;architecture work of count60 issignal bufh:std_logic_vector(7 downto 4);signal bufl:std_logic_vector(3 downto 0);begin process(clk) begin if clr=0 then bufh=0000; bufl=0000; elsif(clkevent and clk=1)then if(bufh=0101and bufl=1001)then co=1; bufh=0000; bufl=0000; elsif(bufl=1001)then bufl=
8、0000; bufh=bufh+1; else bufl=bufl+1; co=0; end if; end if; outh=bufh;outl=bufl; end process;end work;24进制library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity count24 is port( clk :in std_logic; co: out std_logic; outh :out std_logic_vector(7 d
9、ownto 4); outl :out std_logic_vector(3 downto 0); end count24 ;architecture a of count24 issignal bufh:std_logic_vector(7 downto 4);signal bufl:std_logic_vector(3 downto 0);begin process(clk) begin if(clkevent and clk=1)then if(bufh=0010and bufl=0011)then co=1; bufh=0000; bufl=0000; elsif(bufl=1001)
10、then bufl=0000; bufh=bufh+1; else bufl=bufl+1; co=0; end if; end if;outh=bufh; outl=bufl;end process； end a;keyen.vhdlibrary ieee;use ieee.std_logic_1164.all;entity keyen is port(en, keyin:in std_logic; keyout: out std_logic);end keyen;architecture work of keyen isbegin process(en,keyin) begin if en
11、=1 then keyout=keyin; else keyout=0; end if; end process; end work;chose21.vhdlibrary ieee;use ieee.std_logic_1164.all;entity chose21 is port(clk,add,chose : in std_logic; co : out std_logic);end chose21;architecture work of chose21 isbegin process(chose,clk,add) begin if chose=1 then co=clk; else c
12、o=add; end if; end process; end work;3. 闹钟模块：主要功能记录闹钟时间信息，输出闹钟时间信息源代码:同上:keyen.vhd count60.vhd count24.vhd4. 辅控模块：主要功能处理显示，以及蜂鸣器的信号。时钟输入与闹钟输入相比较，组成闹钟功能，以及整点报时功能。源代码Ac.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ac is port(clk,lightonoff:in std_logic; mode,kmode
13、:in std_logic_vector(1 downto 0); csh,csl,cmh,cml,chh,chl,ash,asl,amh,aml,ahh,ahl:in std_logic_vector(3 downto 0); q0,q1,q2,q3,q4,q5,q6,q7:out std_logic_vector(3 downto 0); lightswitch,sound512,sound1024,timeok:out std_logic);end ac;architecture work of ac issignal q0b,q1b,q2b,q3b,q4b,q5b,q6b,q7b: s
14、td_logic_vector(3 downto 0);begin process(chh,cmh,csh,ash,ahh,amh,chl,cml,csl,asl,ahl,aml,mode,kmode,clk) beginif mode=00 or mode=01 then -闪烁功能开始q0b=csl; q1b=csh; q2b=1010; q3b=cml; q4b=cmh; q5b=1010; q6b=chl; q7b=chh; elsif mode=10 or mode=11 then q0b=asl; q1b=ash; q2b=1010; q3b=aml; q4b=amh; q5b=1
15、010; q6b=ahl; q7b=ahh; end if;if clk =1 then if mode=00 or mode=10 then q0=q0b; q1=q1b; q2=q2b; q3=q3b; q4=q4b; q5=q5b; q6=q6b; q7 q0=1111; q1=1111; q2=q2b; q3=q3b; q4=q4b; q5=q5b; q6=q6b; q7 q0=q0b; q1=q1b; q2=q2b; q3=1111; q4=1111; q5=q5b; q6=q6b; q7 q0=q0b; q1=q1b; q2=q2b; q3=q3b; q4=q4b; q5=q5b;
16、 q6=1111; q7 q0=1111; q1=1111; q2=1111; q3=1111; q4=1111; q5=1111; q6=1111; q7=1111; end case; end if; else q0=q0b; q1=q1b; q2=q2b; q3=q3b; q4=q4b; q5=q5b; q6=q6b; q7=q7b; end if; -闪烁功能完毕 -整点报时功能开始 if cmh=0101 and cml=1001 then if csh=0101 then if csl=0001 or csl=0010 or csl=0101 or csl=0111 then so
17、und512=1 ; elsif csl=1001 then sound1024=1; else sound512=0; sound1024=0; end if; end if; end if; -正点报时功能完 -显示开关功能开始 if lightonoff=1 then lightswitch=0; else lightswitch=1; end if; -显示开关功能完毕 -闹钟功能开始 if chh=ahh and cmh=amh and chl=ahl and cml=aml then timeok=1; else timeokqqqqqqqqq=XXXX; end case; en
18、d process； end behave;BCD7DIS.vhdlibrary ieee;use ieee.std_logic_1164.all;entity bcd7dis is port(bcdm :in std_logic_vector(3 downto 0); a,b,c,d,e,f,g : out std_logic);end bcd7dis;architecture art of bcd7dis issignal w : std_logic_vector(6 downto 0);begin process(bcdm) begin a=w(6);b=w(5);c=w(4);d=w(
19、3);e=w(2);f=w(1);gwwwwwwwwwwww= 0000001; end case; end process;end art;SWSC.vhdlibrary ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity swsc is port (en,clk:in std_logic; q: out std_logic_vector(2 downto 0);end swsc;architecture work of swsc isbegin process(clk,en) variable x
20、:std_logic_vector(2 downto 0); begin if (clkevent and clk=1) then if en=1 then if(x0); end if; end if; end if; q=x; end process;end work;3-8译码器实验源码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY YM38 IS PORT (A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); EN:IN STD_LOGIC; Y:OUT
21、STD_LOGIC_VECTOR(7 DOWNTO 0) );END YM38;ARCHITECTURE BEHAV OF YM38 ISSIGNAL CLK: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINCLK Y Y Y Y Y Y Y Y Y=00000000; END CASE; END PROCESS； ENDBEHAV; 6. 蜂鸣模块：主要功能：系统输入只要求一个1024HZ的脉冲信号，分频器模块将1024HZ分为1HZ，4HZ，512HZ，1024HZ，供各个模块使用。源代码Clkcut.vhdlibrary ieee;use ieee.std_logi
22、c_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity clkcut is port(clk:in std_logic; clk1,clk4,clk512,clk1024:out std_logic);end clkcut;architecture work of clkcut issignal w:std_logic_vector(9 downto 0);begin process(clk) begin if clkevent and clk=1 then w=w+1; end if; clk1=w(9); clk4=w(7); clk512=w(0); clk1024=clk; end process;end work;
