1、硬件基础微程序控制器实验报告大学HUNAN UNIVERSITY 硬件基础实验2 实验报告 1、实验预习 1.书中的图形实现微程序控制器,中间的映射逻辑究竟是怎么实现的? 答:但出现分支时,预设端信号由IR决定。IR为1时信号有效,输出为1. 通过IR的值映射为下址的低三位,从而产生下址。 2.书中设计用到了强写强读,为什么要设计这个功能? 答:满足用户因为没有初始化mif文件时输入数据的需要。2、实验目的 微程序控制器实验的主要任务:生成CPU里的控制信号,并使程序按正 确的顺序执行。核心部分是ROM,存放机器指令的微程序。 1、掌握微程序控制器的组成、工作原理; 2、掌握微程序控制器的基本
2、概念和术语:微命令、微操作、微指令、微 程序等; 3、掌握微指令、微程序的设计及调试方法; 4、通过单步运行若干条微指令,深入理解微程序控制器的工作原理;二、实验电路 图1附:电路图过大,请放大观察详情三、实验原理 将机器指令的操作(从取指到执行)分解为若干个更基本的微操作序列,并将有 关的控制信息(微命令)以微码的形式编成微指令输入到控制存储器中。这样, 每条机器指令将与一段微程序对应,取出微指令就产生微命令,以实现机器指令 要求的信息传送与加工。四、实验步骤及概述 1)设计状态机部分 a、编写VHDL代码如下LIBRARY ieee;USE ieee.std_logic_1164.all;
3、ENTITY zhuangtaiji IS PORT ( reset : IN STD_LOGIC := 0; clock : IN STD_LOGIC; qd : IN STD_LOGIC := 0; dp : IN STD_LOGIC := 0; tj : IN STD_LOGIC := 0; t1 : OUT STD_LOGIC; t2 : OUT STD_LOGIC; t3 : OUT STD_LOGIC; t4 : OUT STD_LOGIC );END zhuangtaiji;ARCHITECTURE BEHAVIOR OF zhuangtaiji IS TYPE type_fst
4、ate IS (idle,st1,s_st2,st4,st2,st3,s_st4,s_st3); SIGNAL fstate : type_fstate; SIGNAL reg_fstate : type_fstate;BEGIN PROCESS (clock,reset,reg_fstate) BEGIN IF (reset=1) THEN fstate = idle; ELSIF (clock=1 AND clockevent) THEN fstate = reg_fstate; END IF; END PROCESS; PROCESS (fstate,qd,dp,tj) BEGIN t1
5、 = 0; t2 = 0; t3 = 0; t4 IF (NOT(qd = 1) THEN reg_fstate = st1; ELSE reg_fstate = idle; END IF; t1 = 0; t2 = 0; t3 = 0; t4 IF (tj = 1) AND NOT(dp = 1) THEN reg_fstate = st1; ELSIF (dp = 1) AND NOT(tj = 1) THEN reg_fstate = s_st2; ELSE reg_fstate = st2; END IF; t1 = 1; t2 = 0; t3 = 0; t4 IF (tj = 1)
6、THEN reg_fstate = s_st2; ELSE reg_fstate = s_st3; END IF; t1 = 0; t2 = 1; t3 = 0; t4 IF (tj = 1) AND NOT(dp = 1) THEN reg_fstate = st4; ELSIF (dp = 1) AND NOT(tj = 1) THEN reg_fstate = idle; ELSE reg_fstate = st1; END IF; t1 = 0; t2 = 0; t3 = 0; t4 IF (tj = 1) AND NOT(dp = 1) THEN reg_fstate = st2;
7、ELSIF (dp = 1) AND NOT(tj = 1) THEN reg_fstate = s_st3; ELSE reg_fstate = st3; END IF; t1 = 0; t2 = 1; t3 = 0; t4 IF (tj = 1) AND NOT(dp = 1) THEN reg_fstate = st3; ELSIF (dp = 1) AND NOT(tj = 1) THEN reg_fstate = s_st4; ELSE reg_fstate = st4; END IF; t1 = 0; t2 = 0; t3 = 1; t4 IF (tj = 1) THEN reg_
8、fstate = s_st4; ELSE reg_fstate = idle; END IF; t1 = 0; t2 = 0; t3 = 0; t4 IF (tj = 1) THEN reg_fstate = s_st3; ELSE reg_fstate = s_st4; END IF; t1 = 0; t2 = 0; t3 = 1; t4 t1 = X; t2 = X; t3 = X; t4 = X; report Reach undefined state; END CASE; END PROCESS;END BEHAVIOR; b、新建block file选定zhaungtaiji得到电
9、路图 2)设计rom部分 a、编写VHDL代码如下 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY rom IS PORT ( address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (27 DOWNTO 0); END rom; ARCHITECTURE SYN OF rom IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (27 DOWNTO 0); BEGIN sub_wire0= WHEN address= 00000 EL
10、SE WHEN address= 00001 ELSE WHEN address= 00010 ELSE WHEN address= 01001 ELSE WHEN address= 10101 ELSE WHEN address= 10110 ELSE WHEN address= 01010 ELSE WHEN address= 10111 ELSE WHEN address= 11000 ELSE WHEN address= 01011 ELSE WHEN address= 11001 ELSE WHEN address= 11010 ELSE WHEN address= 01100 EL
11、SE WHEN address= 11011 ELSE WHEN address= 01101 ELSE WHEN address= 11100 ELSE WHEN address= 01110 ELSE WHEN address= 00011 ELSE WHEN address= 00100 ELSE WHEN address= 00101 ELSE WHEN address= 00110 ELSE WHEN address= 01111 ELSE WHEN address= 11101 ELSE WHEN address= 11110 ELSE WHEN address= 11111 EL
12、SE WHEN address= 00111 ELSE WHEN address= 01000 ELSE WHEN address= 10011 ELSE WHEN address= 10100 ELSE WHEN address= 10000 ELSE WHEN address= 10001 ELSE ; q = sub_wire0(27 DOWNTO 0); END SYN; b、新建block file选定rom得到电路图 3)、整合电路图 整合电路图如图1所示。 建工程-建立BlockDiagramFile-按照电路图连好电路-保存、编译-建立 VectorWaveformFile-插
13、入引脚-设置波形-保存、仿真。 仿真后的波形如下: 参数设置:Grid Size:50ns End Time:5.0us其具体实现还需要与数据通路结合才能最终进行具体运算。分析ADD的每条微指的指令格式和功能:ADD:为双字长指令。第一字为操作码,第二字为操作数地址,其含义是将R0寄存器的容与存中以A为地址单元的数相加,结果放R0寄存器中。ADD加法指令由 :S3S2S1S0M CnWE A9 A8 A B C A5-A0 a、(PCAR ,PC+1):000000011 101 101 101 000011b、(RAMBUS, BUSAR):000000010 101 111 111 000
14、100C、(RAMBUS ,BUSDR2):000000010 010 111111 000101d、(RODR1):000000011 010 001 000 000110e、((DR1)+(DR2)RO):100101011 000 001 111 000001 共8条微指令组成。a微指令功能是RAM赋给BUS,BUS赋给DR2; S3 S2 S1 S0 M CN 的值为“000000”代表进行自加1运算;A字段“110”代表选择LDAR操作,B字段“110”是选择PC-B操作;UA5-UA0中“000011”代表下一指令的地址为“011”。b微指令功能是RAM赋给BUS,BUS赋给DR2
15、; S3 S2 S1 S0 M CN 的值为“000000”代表进行自加1运算;A字段“110”代表选择LDAR操作,B字段“000”是无选择操作;UA5-UA0中“000100”代表下一指令的地址为“100”。c微指令功能是RAM赋给BUS,BUS赋给DR2; S3 S2 S1 S0 M CN 的值为“000000”代表进行自加1运算;A字段“011”代表选择LDDR2操作,B字段“000”是无选择操作;UA5-UA0中“000101”代表下一指令的地址为“101”。d微指令功能是RO赋给DR1; S3 S2 S1 S0 M CN 的值为“000000”代表进行自加1运算;A字段“010”代表选择LDDR1操作,B字段“001”是选择RS-B操作;UA5-UA0中“000110”代表下一指令的地址为“110”。e微指令功能是DR1+DR2的和赋给R0; S3 S2 S1 S0 M CN 的值为“100101”代表进行加法运算;A字段“001