1、* Rev. 2.11,Removed definition of LCDLOWR (not available at 4xx devices)* Rev. 2.2, Removed unused def of TASSEL2* Rev. 2.3, Removed definitions for BTRESET* Rev. 2.4, added definitions for Interrupt Vectors xxIV*/#ifndef _msp430x41x#define _msp430x41x#ifdef _IAR_SYSTEMS_ICC_#ifndef _SYSTEM_BUILD#pr
2、agma system_include#endif#if (_TID_ 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */#error msp430x41x.h file for use with ICC430/A430 only#include #pragma language=extended#define DEFC(name, address) _no_init volatile unsigned char name address;#define DEFW(name, address) _no_init volatile unsigned short nam
3、e address;#define DEFXC volatile unsigned char#define DEFXW volatile unsigned short#endif /* _IAR_SYSTEMS_ICC_ */#ifdef _IAR_SYSTEMS_ASM_#define DEFC(name, address) sfrb name = address;#define DEFW(name, address) sfrw name = address;#endif /* _IAR_SYSTEMS_ASM_*/#ifdef _cplusplus#define READ_ONLY#els
4、e#define READ_ONLY const/* STANDARD BITS*/#define BIT0 (0x0001)#define BIT1 (0x0002)#define BIT2 (0x0004)#define BIT3 (0x0008)#define BIT4 (0x0010)#define BIT5 (0x0020)#define BIT6 (0x0040)#define BIT7 (0x0080)#define BIT8 (0x0100)#define BIT9 (0x0200)#define BITA (0x0400)#define BITB (0x0800)#defin
5、e BITC (0x1000)#define BITD (0x2000)#define BITE (0x4000)#define BITF (0x8000)* STATUS REGISTER BITS#define C (0x0001)#define Z (0x0002)#define N (0x0004)#define V (0x0100)#define GIE (0x0008)#define CPUOFF (0x0010)#define OSCOFF (0x0020)#define SCG0 (0x0040)#define SCG1 (0x0080)/* Low Power Modes c
6、oded with Bits 4-7 in SR */#ifndef _IAR_SYSTEMS_ICC /* Begin #defines for assembler */#define LPM0 (CPUOFF)#define LPM1 (SCG0+CPUOFF)#define LPM2 (SCG1+CPUOFF)#define LPM3 (SCG1+SCG0+CPUOFF)#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)/* End #defines for assembler */#else /* Begin #defines for C */#define
7、LPM0_bits (CPUOFF)#define LPM1_bits (SCG0+CPUOFF)#define LPM2_bits (SCG1+CPUOFF)#define LPM3_bits (SCG1+SCG0+CPUOFF)#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */#define LPM1
8、_BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3
9、 */#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */#endif /* End #defines for C */* PERIPHERAL FILE MAP* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL B
10、ITS#define IE1_ (0x0000) /* Interrupt Enable 1 */DEFC( IE1 , IE1_)#define WDTIE (0x01)#define OFIE (0x02)#define NMIIE (0x10)#define ACCVIE (0x20)#define IFG1_ (0x0002) /* Interrupt Flag 1 */DEFC( IFG1 , IFG1_)#define WDTIFG (0x01)#define OFIFG (0x02)#define NMIIFG (0x10)#define IE2_ (0x0001) /* Int
11、errupt Enable 2 */DEFC( IE2 , IE2_)#define BTIE (0x80)#define IFG2_ (0x0003) /* Interrupt Flag 2 */DEFC( IFG2 , IFG2_)#define BTIFG (0x80)* WATCHDOG TIMER#define _MSP430_HAS_WDT_ /* Definition to show that Module is available */#define WDTCTL_ (0x0120) /* Watchdog Timer Control */DEFW( WDTCTL , WDTC
12、TL_)/* The bit names have been prefixed with WDT */#define WDTIS0 (0x0001)#define WDTIS1 (0x0002)#define WDTSSEL (0x0004)#define WDTCNTCL (0x0008)#define WDTTMSEL (0x0010)#define WDTNMI (0x0020)#define WDTNMIES (0x0040)#define WDTHOLD (0x0080)#define WDTPW (0x5A00)/* WDT-interval times 1ms coded wit
13、h Bits 0-2 */* WDT is clocked by fSMCLK (assumed 1MHz) */#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTC
14、L+WDTIS1+WDTIS0) /* 0.064ms /* WDT is clocked by fACLK (assumed 32KHz) */#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms #define WDT_ADLY_1_9
15、(WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms /* Watchdog mode - reset after expired time */#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms #define WDT_MRST_0_064 (WDT
16、PW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms /* INTERRUPT C
17、ONTROL */* These two bits are defined in the Special Function Registers */* #define WDTIE 0x01 */* #define WDTIFG 0x01 */* DIGITAL I/O Port1/2#define _MSP430_HAS_PORT1_ /* Definition to show that Module is available */#define _MSP430_HAS_PORT2_ /* Definition to show that Module is available */#defin
18、e P1IN_ (0x0020) /* Port 1 Input */READ_ONLY DEFC( P1IN , P1IN_)#define P1OUT_ (0x0021) /* Port 1 Output */DEFC( P1OUT , P1OUT_)#define P1DIR_ (0x0022) /* Port 1 Direction */DEFC( P1DIR , P1DIR_)#define P1IFG_ (0x0023) /* Port 1 Interrupt Flag */DEFC( P1IFG , P1IFG_)#define P1IES_ (0x0024) /* Port 1
19、 Interrupt Edge Select */DEFC( P1IES , P1IES_)#define P1IE_ (0x0025) /* Port 1 Interrupt Enable */DEFC( P1IE , P1IE_)#define P1SEL_ (0x0026) /* Port 1 Selection */DEFC( P1SEL , P1SEL_)#define P2IN_ (0x0028) /* Port 2 Input */READ_ONLY DEFC( P2IN , P2IN_)#define P2OUT_ (0x0029) /* Port 2 Output */DEF
20、C( P2OUT , P2OUT_)#define P2DIR_ (0x002A) /* Port 2 Direction */DEFC( P2DIR , P2DIR_)#define P2IFG_ (0x002B) /* Port 2 Interrupt Flag */DEFC( P2IFG , P2IFG_)#define P2IES_ (0x002C) /* Port 2 Interrupt Edge Select */DEFC( P2IES , P2IES_)#define P2IE_ (0x002D) /* Port 2 Interrupt Enable */DEFC( P2IE ,
21、 P2IE_)#define P2SEL_ (0x002E) /* Port 2 Selection */DEFC( P2SEL , P2SEL_)* DIGITAL I/O Port3/4#define _MSP430_HAS_PORT3_ /* Definition to show that Module is available */#define _MSP430_HAS_PORT4_ /* Definition to show that Module is available */#define P3IN_ (0x0018) /* Port 3 Input */READ_ONLY DE
22、FC( P3IN , P3IN_)#define P3OUT_ (0x0019) /* Port 3 Output */DEFC( P3OUT , P3OUT_)#define P3DIR_ (0x001A) /* Port 3 Direction */DEFC( P3DIR , P3DIR_)#define P3SEL_ (0x001B) /* Port 3 Selection */DEFC( P3SEL , P3SEL_)#define P4IN_ (0x001C) /* Port 4 Input */READ_ONLY DEFC( P4IN , P4IN_)#define P4OUT_
23、(0x001D) /* Port 4 Output */DEFC( P4OUT , P4OUT_)#define P4DIR_ (0x001E) /* Port 4 Direction */DEFC( P4DIR , P4DIR_)#define P4SEL_ (0x001F) /* Port 4 Selection */DEFC( P4SEL , P4SEL_)* DIGITAL I/O Port5/6#define _MSP430_HAS_PORT5_ /* Definition to show that Module is available */#define _MSP430_HAS_
24、PORT6_ /* Definition to show that Module is available */#define P5IN_ (0x0030) /* Port 5 Input */READ_ONLY DEFC( P5IN , P5IN_)#define P5OUT_ (0x0031) /* Port 5 Output */DEFC( P5OUT , P5OUT_)#define P5DIR_ (0x0032) /* Port 5 Direction */DEFC( P5DIR , P5DIR_)#define P5SEL_ (0x0033) /* Port 5 Selection */DEFC( P5SEL , P5SEL_)#define P6IN_ (0x0034) /* Port 6 Input */READ_ONLY DEFC( P6IN , P6IN_)#define P6OUT_ (0x0035) /* Port 6 Output */DEFC( P6OUT , P6OUT_)#define P6DIR_ (0x0036) /* Port 6 Direction */DEFC( P6DIR , P6DIR